- Easy high-level and assembler debugging
- Interface to all compilers
- RTOS awareness
- Interface to all hosts
- Fast download
- Display of internal and external peripherals at a logical level
- Flash programming
- Hardware breakpoints and trigger (if supported by on chip debug interface)
- Multiprocessor/multicore debugging
- Trace and trigger extension possible
- Software trace
- Virtual analyzer
- Software compatible to all TRACE32 tools
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- 1, 2 or 4 GByte trace memory
- Universal trace module, connect to target via architecture-dependent trace probes (Preprocessor)
- Support for all parallel trace ports up to 19.2 Gbit/s, e.g. 16 bit up to 300MHz DDR sample rate
- Support for serial trace ports up to 4 lanes, each lane max. 6.5 Gbit/s
- Support for streaming up to 1.6 Gbit/s
- Additional independent 17 channel logic analyzer (with Standard Probe)
- Energy Profiling (with optional Analog Probe)
- PODBUS Express interface to PowerDebug PRO (successor of PowerDebug II)
- PODBUS and PODBUS Express interfaces to Logic Analyzer modules, e.g. PowerProbe, PowerIntegrator
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- Support for NEXUS standard class 1 to 3+
- Programming support for on-chip and external flashes
- Real-time access to memory
- Hardware breakpoints and trigger
- Program and data flow trace up to 400 MHz
- Up to 4 GByte trace memory
- Upload to host within 10 seconds typically
- Selective data flow trace for 2 address ranges
- Trigger on instruction execution or data access
- Statistic functions/Performance analysis
- Code coverage
- External trigger input and output
- USB and ETHERNET interface included
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- Compatible with Emulator
- Support for C,C++ and ASM
- Communication via Eprom Simulator
- Communication via RS232 or customized .DLL link
- Windows9x, WindowsNT and Unix
- Monitor Code with Source
- Monitor Code Royalty Free
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- Integral part of TRACE32
- Configurable as system under debug (PBI=SIM)
- Allows post-mortem debugging
- Software compatible to all TRACE32 tools
- Easy high-level and assembler debugging
- OS-aware debugging
- Cache simulation (architecture dependent)
- Program and data flow trace based on a bus trace protocol
- Advanced trace analysis features
- Powerful script language
- Programming interface for peripheral simulation
- Not available for the MIPS architecture
- Not available for processor architectures that support user-defined instructions
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