TRACE32® CombiProbe 2 MIPI60-Cv2

Tool Configuration

Adaptation

TRACE32 Debug Features

Highlights

	CombiProbe MIPI60-Cv2 provides debug and system trace capability
	Support for standard JTAG, debug HOOKs and I2C bus
	Support for merged debug ports (two JTAG chains per debug connector)
	Support for survivability features (threshold, slew rate, etc.)
	Support for system trace port with up to 8 trace data channels
	512 MByte of trace memory
	Voltage range 1.0 V to 1.8 V

	SMP debugging (including hyperthreading)
	AMP debugging with other architectures
	BIOS/UEFI debugging with tailor-made GUI for all UEFI phases
	Linux- and Windows-aware debugging
	Hypervisor debugging
	Support for system trace decoding via the Intel® Trace Hub Library
	AUTOSAR aware debugging and profiling


List of Supported Compilers List of Supported Target Operating Systems List of Supported UEFIs List of Supported Hypervisors

Tool Configuration

The photo on the left side shows a standard configuration. The extended configuration shown on the right side allows to record additionally Intel® Processor Trace data conveyed off-chip.

Adaptation

Adaptation for CombiProbe MIPI60-Cv2

TRACE32 Debug Features

Multicore Debugging

Debugger for all cores of a multicore chip / multiprocessor system
Debugging of high-performance and real-time cores, DSPs, accelerator and special-purpose cores
Support for every multicore topology
Support for all multicore operation modes
Support for AMP, iAMP and SMP systems
Single debug hardware can be licensed for all cores of a multicore chip / multiprocessor system

Debug Support for Unified EFI Bootloader

Support by a loadable extension
Debug support for all UEFI phases
Tailor-made display windows for each UEFI phase
Continuous solution without "debug gap"
Debugging from reset vector
Debugging of dynamically loaded drivers from their entry point

OS-aware Debugging

Real-time, non-intrusive display of RTOS system resources
Task stack coverage
Task related breakpoints
Task context display
SMP support
Task related performance measurement
Statistic evaluation and graphic display of task run times
Task related evaluation of function run times
PRACTICE functions for OS data
Easy access via RTOS specific pull-down menus
Support for all major RTOSes

Hypervisor-aware Debugging

Seamless debugging of the total system in stop-mode
Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
Hypervisor-aware debugging for high-performance cores (MMU) such as Arm Cortex, PowerArchitecture and Intel x64
Hypervisor-aware debugging for selected real-time cores (MPU) such as Arm Cortex-R52/-R82, RH850 (G4MH4 core and later) and TriCore TC4x
Machine ID allows the user to uniquely identify any virtual machine in the system
Machine ID provides full visibility of context of active and inactive virtual machines
OS-awareness can be loaded for each virtual machine

AUTOSAR-Aware Debugging: Adaptive Platform

Single-core and SMP operating systems
Debug support for standard rich OSes such a eMCOS. Linux, PikeOS, QNX
Standardized, OS-independent list display of AUTOSAR Adaptive Applications

ARTI-Compliant Profiling of AUTOSAR Adaptive Platform

STM based task state profiling
AUTOSAR ARTI compliant
TRACE32 Streaming enables very long recording times

Script Language PRACTICE

Structured Language
Menu Support
Command Logs
Custom Menues
Custom Toolbars and Buttons
Custom Dialog Windows
64-Bit Arithmetic
Numeric, Logical and String Operators
Direct Access to System States

Intel and the Intel logo are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

Copyright © 2023 Lauterbach GmbH, Altlaufstr.40, 85635 Höhenkirchen-Siegertsbrunn, Germany Impressum Privacy Policy
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 13-Jan-2023