CombiProbe 2 Intel® Direct Connect Interface (Intel® DCI) OOB

The embedded tools company
Tool Configuration
DCI OOB Protocol
TRACE32 Debug Features

CombiProbe 2 Intel® Direct Connect Interface (Intel® DCI) OOB
CombiProbe DCI OOB for closed chassis targets with USB3 port and DCI OOB capability
CombiProbe DCI OOB provides debug and system trace capability
Support for standard JTAG, debug HOOKs and system trace via DCI protocol
512 MByte of trace memory

SMP debugging (including hyperthreading)
AMP debugging with other architectures
BIOS/UEFI debugging with tailor-made GUI for all UEFI phases
Linux- and Windows-aware debugging
Hypervisor debugging
System trace configuration and decoding via the Intel® Trace Hub library

List of Supported Compilers
List of Supported Target Operating Systems
List of Supported UEFIs
List of Supported Hypervisors


Tool Configuration

Configuration of CombiProbe for Intel Processors

The photo on the left side shows the TRACE32 standard configuration with USB3 as host interface. The photo on the right side shows the TRACE32 configuration for Gigabit Ethernet.

DCI OOB Protocol

Debug commands entered via the TRACE32 PowerView GUI are converted by TRACE32 into JTAG commands and wrapped into the DCI OOB protocol. TRACE32 sends these commands to the target system.

TRACE32 configuration

In the target system the commands are decoded by the OOB module and forwarded to the DCI bridge. The DCI bridge on the target side unwraps the DCI packets and passes the JTAG commands to the appropriate TAP/CPU. The communication between the target and the tool traverses the same path backwards.

Trace data can be exported through the DCI bridge/OOB module and are recorded by the CombiProbe.

DCI protocol


For using DCI OOB, the USB part of your target system must be electrically designed such that DCI OOB signaling is not blocked. This is of special importance for USB Type-C solutions. Details about these requirements can be found in the appropriate Intel Platform Design Guide.

TRACE32 Debug Features

Multicore Debugging
  • Debugger for all cores of a multicore chip / multiprocessor system
  • Debugging of high-performance and real-time cores, DSPs, accelerator and special-purpose cores
  • Support for every multicore topology
  • Support for all multicore operation modes
  • Support for AMP, iAMP and SMP systems
  • Single debug hardware can be licensed for all cores of a multicore chip / multiprocessor system

Debug Support for Unified EFI Bootloader
  • Support by a loadable extension
  • Debug support for all UEFI phases
  • Tailor-made display windows for each UEFI phase
  • Continuous solution without "debug gap"
  • Debugging from reset vector
  • Debugging of dynamically loaded drivers from their entry point

OS-aware Debugging
  • Real-time, non-intrusive display of RTOS system resources
  • Task stack coverage
  • Task related breakpoints
  • Task context display
  • SMP support
  • Task related performance measurement
  • Statistic evaluation and graphic display of task run times
  • Task related evaluation of function run times
  • PRACTICE functions for OS data
  • Easy access via RTOS specific pull-down menus
  • Support for all major RTOSes

Script Language PRACTICE
  • Structured Language
  • Menu Support
  • Command Logs
  • Custom Menues
  • Custom Toolbars and Buttons
  • Custom Dialog Windows
  • 64-Bit Arithmetic
  • Numeric, Logical and String Operators
  • Direct Access to System States

Intel and the Intel logo are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.

Copyright © 2023 Lauterbach GmbH, Altlaufstr.40, 85635 Höhenkirchen-Siegertsbrunn, Germany   Impressum     Privacy Policy
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 02-Jan-2023