Timing and Protocol Analyzer


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Picture
  Highlights
Timing analyzer up to 200 MHz
Time correlation with state analyzer
Selective trace controlled by state analyzer
State analyzer mode
16 channel pattern generator
2 channel serial line tester
 
  Introduction
The Timing- and Protocol Analyzer Module TA32 is special designed for microprocessor applications. It can work separately or in conjunction with the state analyzer module HA120. The high-speed transient recording allows very long record time when tracing peripheral lines in a microcontroller application.


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Features


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Logic Analyzer Module


Basics

The Timing Analyzer is specially designed for microprocessor applications. The modul supports timing and state analysis, pattern generation and serial interface test (V.24).

Max. 32 Channels

5 operating modes:
  • 32 channel asynchronous 50 MHz
  • 16 channel asynchronous 100 MHz
  • 8 channel asynchronous 200 MHz
  • 31 channel synchronous 15 MHz clock
  • Mixed mode (state/timing)

Transient Recording over required Time

The recording depth is governed by the number of transitions on the transient sensitive inputs.

High Memory Depth

  • minimum 32K transients at 50MHz
  • minimum 160 us capture time

Transient Sensitivity can be activated independently for each Group

Time Stamp with 20ns Resolution in synchronous Modes

Time Correlation with all other Clocks and Analyzers of the System

31 Clock Qualifiers in Synchronous Mode

The clock qualifier inputs can be synchronised with the input clock (no AND function with the input clock)

Master-Slave Operation in Conjunction with other Analyzers

Trigger Conditions

  • HIGH, LOW or DON'T CARE for each input
  • Range trigger definitions for each group

4 Trigger Events

  • 4 global event, no death time
  • 4 events on every trigger level with 20ns death time

Trigger Filter

Freely programmable Trigger Sequencer

Input variables
  • Trigger events A,B,C
  • Bus trigger lines 0 to 3 (as inputs)
  • Event counter actions/operations
  • Acquisition ON/OFF
  • Trigger
  • Bus trigger lines 0...3
  • Counter enable
  • Counter restart
  • Sequential triggering through 8 levels

Two retriggerable 48 Bit Counters in Trigger System

  • Time window definition

Triggering through Bus Trigger Lines

Programmable Trigger Delay 0 to 100% of Records

Triggering of other System Units

Trigger Output for Oscilloscope etc.

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Option Pattern Generator


16 Channels

100ns Cycle Time

External/Internal Clock

  • 10 MHz internal
  • 0..10 MHz external
  • Rising/falling edge
  • Single step

Clock Qualifier

  • High
  • Low
  • Don't care

Trigger Latch Mode

  • Stores trigger event

Trigger Input

  • BUS A..D
  • External D.3
  • External D.4
  • Serial line tester
  • Trigger mode
  • High
  • Low
  • Rising
  • Falling

Clock Enable Input

Trigger Output to BUS

  • BUS A..D

Retrigger Function

  • Wait for trigger
  • Restart

Pattern Definition

  • Standby
  • Set
  • Repeat
  • ()
  • Delay
  • Wait
  • Restart
  • Stop

Pattern Display

  • List Mode
  • Timing Mode
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Option Serial Line Tester


2 Channels

Baudrate

  • 50-76800

Transfer Mode

  • Even/odd
  • 5..8 bit
  • 1..2 stop bit

Operation Modes

  • Terminal operation
  • DUMP operation
  • Connection to Timing Analyzer
  • Connection to Pattern Generator
  • File transfer
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Probes


CIN8

  • Logic input probe

CREF8

  • Logic input probe with variable threshold level

COUT8

  • Output probe

Clip Set

  • Test cables




Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 28-Jan-2016