PowerIntegrator - Logic and Bus Analyzer

Logic Analyzer

Debugger with Target for ARM9 and 204-Channel Logic-Analyzer

Single MICTOR Probe

Basics

The PowerIntegrator Logic Analyzer is specially designed for microprocessor system integrations. The modul supports timing and state analysis up to 500 MHz.

Fast Upload

• 500 KBytes/sec

Time Stamp Unit with 4ns Resolution

Time Correlation with all other Clocks and Analyzers of the System

Master-Slave Operation in Conjunction with other Analyzers

Timing Analyzer

Input Channels

• 102 channels timing mode 500 MHz 1024K Records
• 204 channels timing mode 250 MHz 512K Transients

Transient Recording over required Time

High Memory Depth

• 256K low speed timing transients or state edges

Transient sensitivity can be activated independently for each channel

State Analyzer

Input Channels

• 204 channels state mode 200 MHz 512K Trace (clock A or B)
• 102 channels state mode 200 MHz 512K Trace (clock A or B) Double Data Rate
• 102 channels state mode 200 MHz 512K Trace (clock A or B) and
• 102 channels state mode 200 MHz 512K Trace (clock J or K)
• sampling on rising or falling clock edge,

Direct Integration in Debugger Software

Complex Bus Oriented Triggering

Trigger

Simple Trigger

• 1 Complex comparator with HIGH, LOW, RISING, FALLING or DON'T CARE for each input
• More than one clock edges can be selected for trigger condition
  
• Direct setting in timing display window
  
  

Complex Trigger

• Free programmable trigger sequencer with 4 levels

Trigger Events

• 2 Trigger comparators with 64 Bit each on every trigger level with HIGH, LOW, DON'T CARE and RANGE
• 8 Address Selectors with 32-Bit Range

4 Trigger Levels

• 4 global event, no death time

Trigger Filter

• Up to 2.5 us

3 Retriggerable 44 Bit Counters in Trigger System

• Time window definition

Trigger Output for Scope etc.

Triggering through Bus Trigger Lines

Programmable Trigger and Pretrigger Delay 0 to 1000% of Records

Triggering of other System Units

Trigger Output for Scope etc.

Trigger Input

• BUS
• External
• Trigger mode
  • High
  • Low
  • Rising
  • Falling

Formats

Various storage formats

• Binary
• VHDL
• Verilog

Protocol Support

プロトコル解析

CAN サポート USB サポート I2C サポート JTAG サポート ASYNC サポート ユーザ定義プロトコル

Disassembler Support

• Many disassemblers can be selected for bus trace operations

Probes

MICTOR Probe 34 channel MICTOR probe (32 Data, 2 Clocks) Selectable threshold level for groups of 17 lines (16 Data, 1 Clock) 0.1..5.0 V 50 KOhm/4 pF 0..5 V with probe compensation		Signal Pin   Pin Signal         N/C 1 2 N/C GND 3 4 N/C CLK0 5 6 CLK1 D15 7 8 D31 D14 9 10 D30 D13 11 12 D29 D12 13 14 D28 D11 15 16 D27 D10 17 18 D26 D9 19 20 D25 D8 21 22 D24 D7 23 24 D23 D6 25 26 D22 D5 27 28 D21 D4 29 30 D20 D3 31 32 D19 D2 33 34 D18 D1 35 36 D17 D0 37 38 D16         Connect Pin 39,40,41,42 and 43 to GND
MICTOR Differential Clock Probe 33 channel MICTOR probe (32 Data, 1 Clock Pair) Selectable threshold level for groups of 16 lines 0.1..5.0 V 50 KOhm/4 pF 0..5 V with probe compensation		Signal Pin   Pin Signal         N/C 1 2 N/C GND 3 4 N/C CLK+ 5 6 CLK- D15 7 8 D31 D14 9 10 D30 D13 11 12 D29 D12 13 14 D28 D11 15 16 D27 D10 17 18 D26 D9 19 20 D25 D8 21 22 D24 D7 23 24 D23 D6 25 26 D22 D5 27 28 D21 D4 29 30 D20 D3 31 32 D19 D2 33 34 D18 D1 35 36 D17 D0 37 38 D16         Connect Pin 39,40,41,42 and 43 to GND
MICTOR Differential Probe 17 channel MICTOR probe (16 Data Pairs, 1 Clock Pair) 0.1..5.0 V 50 KOhm/4 pF 0..5 V with probe compensation		Signal Pin   Pin Signal         N/C 1 2 N/C GND 3 4 N/C CLK+ 5 6 CLK- D15+ 7 8 D15- D14+ 9 10 D14- D13+ 11 12 D13- D12+ 13 14 D12- D11+ 15 16 D11- D10+ 17 18 D10- D9+ 19 20 D9- D8+ 21 22 D8- D7+ 23 24 D7- D6+ 25 26 D6- D5+ 27 28 D5- D4+ 29 30 D4- D3+ 31 32 D3- D2+ 33 34 D2- D1+ 35 36 D1- D0+ 37 38 D0-         Connect Pin 39,40,41,42 and 43 to GND
SAMTEC Probe 34 channel SAMTEC probe (32 Data, 2 Clocks) Selectable threshold level for groups of 17 lines (16 Data, 1 Clock) 0.1..5.0 V 50 KOhm/4 pF 0..5 V with probe compensation		Signal Pin   Pin Signal         GND 1 2 GND N/C 3 4 N/C GND 5 6 GND D16 7 8 D0 GND 9 10 GND D17 11 12 D1 GND 13 14 GND D18 15 16 D2 GND 17 18 GND D19 19 20 D3 GND 21 22 GND D20 23 24 D4 GND 25 26 GND D21 27 28 D5 GND 29 30 GND D22 31 32 D6 GND 33 34 GND D23 35 36 D7 GND 37 38 GND D24 39 40 D8 GND 41 42 GND D25 43 44 D9 GND 45 46 GND D26 47 48 D10 GND 49 50 GND D27 51 52 D11 GND 53 54 GND D28 55 56 D12 GND 57 58 GND D29 59 60 D13 GND 61 62 GND D30 63 64 D14 GND 65 66 GND D31 67 68 D15 GND 69 70 GND N/C 71 72 N/C GND 73 74 GND N/C 75 76 N/C GND 77 78 GND CLK1 79 80 CLK0 GND 81 82 GND N/C 83 84 N/C GND 85 86 GND N/C 87 88 N/C GND 89 90 GND N/C 91 92 N/C GND 93 94 GND GND 95 96 GND N/C 97 98 N/C N/C 99 100 N/C
SAMTEC Differential Clock Probe 33 channel SAMTEC probe (32 Data, 1 Clock Pair) Selectable threshold level for groups of 16 lines 0.1..5.0 V 50 KOhm/4 pF 0..5 V with probe compensation		Signal Pin   Pin Signal         GND 1 2 GND N/C 3 4 N/C GND 5 6 GND D16 7 8 D0 GND 9 10 GND D17 11 12 D1 GND 13 14 GND D18 15 16 D2 GND 17 18 GND D19 19 20 D3 GND 21 22 GND D20 23 24 D4 GND 25 26 GND D21 27 28 D5 GND 29 30 GND D22 31 32 D6 GND 33 34 GND D23 35 36 D7 GND 37 38 GND D24 39 40 D8 GND 41 42 GND D25 43 44 D9 GND 45 46 GND D26 47 48 D10 GND 49 50 GND D27 51 52 D11 GND 53 54 GND D28 55 56 D12 GND 57 58 GND D29 59 60 D13 GND 61 62 GND D30 63 64 D14 GND 65 66 GND D31 67 68 D15 GND 69 70 GND N/C 71 72 N/C GND 73 74 GND N/C 75 76 N/C GND 77 78 GND CLK- 79 80 CLK+ GND 81 82 GND N/C 83 84 N/C GND 85 86 GND N/C 87 88 N/C GND 89 90 GND N/C 91 92 N/C GND 93 94 GND GND 95 96 GND N/C 97 98 N/C N/C 99 100 N/C
Standard Probe 17 channels Selectable threshold level (16 Data, 1 Clock) 0.1..5.0 V 50 KOhm/4 pF 0..5 V with probe compensation		Signal Pin   Pin Signal         N/C 1 2 N/C CLK 3 4 D15 D14 5 6 D13 D12 7 8 D11 D10 9 10 D9 D8 11 12 D7 D6 13 14 D5 D4 15 16 D3 D2 17 18 D1 D0 19 20 GND
Analog Probe 4 Voltage Channels 12 bit 0..5 V, 1 MOhm 3 Current Channels 5% Accuraccy, external Shunt 625 KSampes/sec sampling rate		Signal Pin   Pin Signal         I2- 1 2 GND I2+ 3 4 GND I1- 5 6 GND I1+ 7 8 GND I0- 9 10 GND I0+ 11 12 GND V3 13 14 GND V2 15 16 GND V1 17 18 GND V0 19 20 GND
USB2 Probe Recording of USB2 and USB1.x protocol Filter, trigger and display on PID protcol level
DigRF ProbeSet probe set (3 pieces) for 3G/DigRF protocol differential RX differential TX single ended SysClkEna single ended ANY (for free use)		Signal Pin   Pin Signal         RX+ 1 2 GND N/C 3 4 N/C RX- 5 6 GND         Signal Pin   Pin Signal         TX+ 1 2 GND N/C 3 4 N/C TX- 5 6 GND         Signal Pin   Pin Signal         CLKEN 1 2 GND N/C 3 4 N/C SYSCLK 5 6 GND
DRAM Adapter 184 Pin DIMM 144 Pin SO_SDRAM 200 Pin SO_DDR 200 Pin SO_DDR2		Adaptions for PowerIntegrator Definitions for Evaluation Boards Setup Scripts
Board Adapter Adapters for Tektronix and Agilent Adaptions