News - Lauterbach and SiFive bring support for RISC-V Cores


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Höhenkirchen-Siegertsbrunn, 24-Oct-2017


Lauterbach and SiFive Bring TRACE32 Support for High-Performance RISC-V Cores
World-class microprocessor development tools now available for industry’s leading RISC-V IP

Höhenkirchen-Siegertsbrunn, Germany, and San Mateo, Calif. – Lauterbach, the leading manufacturer of microprocessor development tools, and SiFive, the first fabless provider of customized, open-source-enabled semiconductors, today announced the availability of Lauterbach’s TRACE32 toolset to provide debug capabilities for SiFive’s E31 and E51 RISC-V Core IP, based on the free and open RISC-V ISA. Lauterbach support for SiFive cores is the latest addition to the growing ecosystem of industry-leading development tools to become available for RISC-V based silicon

Founded by the inventors of RISC-V, SiFive IP addresses the need to combat the rapidly increasing cost of designing and manufacturing new chip architectures, and fulfills the company’s mission of democratizing access to custom silicon. Since its launch, SiFive IP has become the de facto leader for RISC-V cores, with more public customers and working silicon in the market than any other RISC-V vendor.

“The addition of Lauterbach’s TRACE32 toolset to the SiFive arsenal is a milestone in the continued development of the RISC-V ecosystem,” said Yunsup Lee, co-founder and chief technology officer, SiFive. “We have worked closely with Lauterbach to ensure that its TRACE32 toolset provides the highest level of support for the RISC-V debug specification. We look forward to our continued collaboration with Lauterbach to bring additional world-class tools for developers working with SiFive IP.”

Lauterbach TRACE32 provides multicore debugging on individual hardware threads of SiFive cores, enabling debugging right from the reset vector, which analyzes startup codes and other key functions. Lauterbach also provides high-level and assembler debugging for a variety of standard ISA extensions, such as compressed instructions and floating point. It also fully supports the JTAG Debug Transport Module (DTM) in all SiFive chips, and has planned support for other debug interfaces such as USB.

“We’ve seen a growing interest in RISC-V across the industry, and we are pleased to extend our leading toolset to this segment of the market,” said Stephan Lauterbach, general manager of Lauterbach. “The availability of TRACE32 debugging tools will help build on the initial success of RISC-V and continue its adoption in a wide array of deployments.”

Said Rick O’Connor, chairman of the RISC-V Foundation: “The addition of Lauterbach’s world-class solutions to the RISC-V toolset is a testament to the market potential of this new approach to silicon design. Continued collaboration between SiFive and Lauterbach will ensure seamless interoperability between RISC-V hardware and TRACE32.”



Additional Information
RTOS Debugger for RISC-V
SiFive´s Core IP



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Last generated/modified: 24-Oct-2017