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Support for ARM Coresight available
Lauterbach, as technology and market leader for JTAG debuggers and ETM
real-time traces supports now CoreSight, the new ARM standard for
debugging and tracing single ARM cores as well as complex multi-core SOCs.
Based on the CoreSight technology Lauterbach offers the following new
features for their ARM JTAG debuggers:
- Memory read and write while the ARM core is executing the program
via the Debug Access Port (DAP).
- A standardized stop synchronization for multi-core SOCīs via the
Embedded Cross Trigger (ECT).
CoreSight offers also extended trace capabilities:
- Multiple trace sources (CoreSight Trace Funnel)
CoreSight allows that several cores share the same external trace port/on-chip ETB to broadcast their program and data flow information.
- Address and data tracing for the AHB bus (HTM32 and HTM64)
All broadcasted trace information is recorded either into the trace memory of
TRACE32-PowerTrace or into the ETB on-chip trace buffer. The job of the
TRACE32 software is now:
- To assign the program and data flow information to the corresponding
core.
- To provide trace control and trigger/filter features separately for each
core.
- To display the AHB bus information in an unattached, separate trace
listing.
The time relationship between the trace information for the individual cores
and the AHB bus can be viewed by using the window tracking mechanism of
TRACE32.
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