NIOS II Trace

NIOS-II ALTERA

Highlights

	up to 4 GByte trace memory
	up to 512 MFrames
	Target voltage 0.4 .. 5.2 V
	20/5 ns time stamp
	Full support for trigger and filter features
	Recontruction of trace gaps in the case of an overflow of the internal FIFO
	Performance analysis
	Function and task run-time measurement
	Code coverage
	Discrete instruction and data trace

		Modules Adaptions Dimensions	Max. Operation Frequency	Operation Voltage	Frequently Asked Questions	Order Information	Technical Support
Debugger for NIOS-II PowerTrace [www.altera.com] Altera NIOS Site

TRACE EXTENSION FOR NIOS-II

The PowerTrace samples all trace port lines up to a speed of 500 MHz into the trace buffer. The maximum size of the trace buffer is 64/128 MFrames (1 frame per clock).

The connection to the target is done by standardized adapters defined by manufacturer. The system can run on PCs or any workstation.

NIOS-II Trace Features For Advanced Debugging

Program Flow Trace

Data Trace

Timestamp

Trace Filter and Trigger

Sample only the specified event
Sample the complete program flow and the specified data event
Switch the sampling to the trace buffer on/off after a specified event occurred

CTS Trace-based Debugging

Single Stepping of realtime programs
Local and global variable display
Stack frame display
Step, Back Step and Stepover
Conditional Stepping
Display of register variables in trace
Display of function nesting with parameters in trace

SmartTrace

Fills in missing code
Direct branch reconstruction
Indirect branch reconstuction with CTS
Memory and Register values from CTS

Energy Profiling

Realtime measurement of 3 current and 4 voltage lines
Realtime trigger on current, voltage and power
Time correlation with other TRACE32 tracetools
Energy statistics on function and task level
Fully integrated in the TRACE32 user interface

RTOS Support

NIOS-II Trace Features For Runtime Analysis

Trace-based Profiling

Detailed analysis of function run-times
Detailed analysis of task run-times and state
Graphical analysis of variable values over the time
Analysis of the time interval of a single event (e.g. Interrupt)
Analysis of the time interval between 2 defined events

Sample-based Profiling

Long-time performance analysis for functions
Long-time performance analysis for tasks
Long-time analysis of the contents of a variable or memory location and more

NIOS-II Trace Features For Quality Assurance And Optimizing

Trace-based Code Coverage

Long-Time Hardware Coverage Analysis for Emulator and ETM
Trace Based Coverage Analysis for ICD and Emulator
Analysis on ASM and HLL
Coverage summary on modul/function level

Cache Analysis

Basic support for all microcontrollers
Advanced support for ARM architecture
Optimize instruction and data cache usage
Find bus transfer bottlenecks
Verify effects of code optimisation
Simulate effects of different cache sizes
Various graphical and numerical displays

Connector

Adaption for Nios II

Application Note

Instantiating the Off-Chip Trace NIOS

Buffer Module for Off-Chip Trace Port

Details and Configurations

NIOS-II

Copyright © 2010 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice.
Last generated/modified: 2-Sep-2010