In-Circuit Emulator for MELPS 7700


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BASE PROBE


Picture
  Highlights
25 MHz no-waitstate emulation
Supports wide speed range (100KHz .. 25MHz)
Support for IAR and MICROTEC C Compiler
RTOS support for embOS and RTOS/7700
Dual ported memory
Internal data memory image
Port analyzer
Powerful performance analysis
Support for 3.3V and 5V targets
Windows9x, NT and Motif support
Support for MELPS37702, MELPS37703, MELPS37704, MELPS37705, MELPS37708, MELPS37710, MELPS37730, MELPS37732, MELPS37733, MELPS37750
 
  Introduction
The TRACE32-ICE MELPS supports most of the members of the Renesas MELPS 7700 family. The emulator uses the emulation chip mode in order to get full access to the internal and external program and data area. A port-replacement unit reconstructs the lower ports transparent to the user. The modular and open technology of ICE-MELPS allows the fast integaration of new chip designs.

TRACE32-ICE is a state of the art In-Circuit Emulator, which offers unlimited hardware breakpoints and up to 16MByte dual-ported emulation memory. The real-time trace and trigger work up to the max. speed of the CPU. The analyzer offers selective trace as well as performance analysis and statistic functions.


Dim
Modules
Adaptions
Dimensions
Freq
Max. Operation Frequency
Volt
Operation Voltage
FAQ
Frequently Asked Questions
Order
Order
Information
Support
Technical Support



TOP

BASE PROBE


Operating Modes

  • Reset Down
  • Reset Up
  • No Probe
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Dual-Port Access

  • No Delay
  • Request
  • Wait
  • Denied

Operation Frequency

  • 100KHz ... 25 MHz

Processor Modes

  • Single-Chip
  • Microprocessor 16 bit bus
  • Microprocessor 8 bit bus
  • Expanded 16 bit bus
  • Expanded 8 bit bus

Operation with external or internal Clock

Internal Clock 0.75 to 25 MHz

Multitask Debugging

  • 10 tasks
  • 1 forground task
  • 1 background task

Wait System

  • Additional wait cycles may be specified

Voltage and Clock Monitors for the Target System

Exception Control

  • Static Exception Setting
  • RESET
  • Target Exception Control
  • RESET
  • HOLD
  • HOLDA
  • READY
  • Exception Trigger
  • RESET
  • HOLD
  • ZERO
  • BRU
  • WDT
  • and all internal interrupts
  • Simulation
  • Exception Simulation
  • RESET
  • HOLD
  • Watchdog timer (disable/enable) by hardware
  • Port Analyzer (optional)




Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 28-Jan-2016