In-Circuit Emulator for ARM7 The embedded tools company
home Products ICE In-Circuit Emulator In-Circuit Emulator for ARM7


In-Circuit Emulator for ARM7

Picture

 
Active, passive and tracking emulation supported
 
Interface for flexible adaption to ARM7TDMI based designs
 
Software compatible JTAG debugger available
 
HLL debugger with C and C++ support
 
Disassembler for ARM and THUMB code
 
Inline assembler for ARM and THUMB code
 
Little and big endian byte ordering
 
Support for pipelined and de-pipelined address timing
 
Operation from 3.0 to 5.0V in passive mode and from 3.0 to 3.6V in active and tracking mode
 
Support for

ARM7TDMI, ARM7TDMI-AMBA

 


The TRACE32-ICEARM supports the ARM7TDMI macrocell with and without AMBA interface. The flexible concept of the probe allows the adaption to customer specific ASICs or to standard microcontrollers. An extensive specification is available that provides a detailed overview of our requirements. Please call or email our techinal support to get this document.


Link Doc
Download full document
icearm.pdf
(198k)		 Dim
Modules
Adaptions
Dimensions		 Freq
Max. Operation Frequency		 Volt
Operation Voltage		 Faq
Frequently Asked Questions		 Order
Order
Information		 Support
Technical Support
[www.arm.com]  ARM Home Page





Emulation Modes

  • Active emulation for evaluation boards or chip with full visibility of all core signals
  • Passive emulation for a very flexible adaption of our emulator to your ASIC
  • Tracking emulation for low speed applications
    Get Document with ASIC Design Hints

Dual-Port Access

  • AMBA Request
  • AMBA High Priority Request
  • Clock Steal
  • Wait Steal
  • No Delay 16
  • No Delay 32

Operation with external or internal Clock

Waitstate Handling

  • Flexible wait cycle insertion in stand alone mode
  • Trace of waitstate counter (4bit)

Voltage and Clock Monitors for the Target System

Exception Control

  • FIQ
  • IRQ
  • ERROR
  • RES0
  • RES1

Exception Simulation

  • FIQ
  • IRQ
  • ERROR
  • RES0
  • RES1
  • CPU RES0
  • CPU RES1




Navigation
Copyright © 2008 Lauterbach Datentechnik GmbH, Fichtenstr. 27, D-85649 Hofolding, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice.
Last generated/modified: Jan-11-2008