In-Circuit Emulator for 93110


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1. ICE 93C110


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1. ICE 93C110


Operating Modes

  • Reset Down
  • Reset Up
  • No Probe
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Dual-Port Access

  • No Delay
  • Clock steal
  • Denied

System Clock

  • Max. operation frequency 15 MHz
  • Operation with external or internal clock
  • Internal clock 0.75 to 35 MHz

Multitask Debugging

  • 10 tasks
  • 1 foreground task
  • 1 background task

Wait System

  • Additional wait cycles (4K blocks globally and bytewise in 64K area)
  • Up to 250 wait cycles (1-15 can be specified)

Voltage and Clock Monitors for the Target System

Separate Breakpoint System for all TRAPs

Single Cycle Operation (WAIT or BR Modes)

Emulation does not use any Memory or TRAPs

Exception Control

  • Static Exception Setting
  • CPU Reset
  • Peripheral Reset
  • Halt
  • Bus Request
  • Target Exception Control
  • Reset
  • Halt
  • Bus Request
  • Bus Error
  • Auto Vector
  • NMI
  • Exception Trigger
  • Reset
  • CPU Reset
  • Halt
  • Bus Request
  • Bus Error
  • Simulation
  • All TRAPs
  • Exception Simulation
  • Peripheral Reset
  • CPU Reset
  • Halt
  • Bus Request
  • Bus Error
  • Rerun

Interrupt Simulation

  • Level-7-Interrupt
  • All TRAPs

Power Consumption

  • 10 W




Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 28-Jan-2016