In-Circuit Emulator for Z80 and Z180


The embedded tools company
ICE 80 BASE


S180 Z180 Z181 Z182

Picture
  Highlights
20 MHz no-waitstate emulation
Interface with C and PLM
RTOS support for CMX-RTX and VRTX80
Banking support up to 256 banks
MMU support
Support for power down mode
Port analyzer
Cost effective 8-bit emulation system
Software compatible ROM-monitor
Support for 8085, HD64180, TMPZ84C00, Z80180, Z80181, Z8400, Z84C50, Z86x08, Z86x21, Z86x30, Z86x40, Z8S180, and more
 
  Introduction
The TRACE32-ICE80 supports most of the members of the Z80- and Z180-family from Zilog and Renesas. Its modular and open technology allows the fast integration of new chip designs.

A software compatible ROM monitor is also available.

TRACE32-ICE is a state of the art In-Circuit Emulator, which offers unlimited hardware breakpoints and up to 16MByte dual-ported emulation memory. The real-time trace and trigger work up to the max. speed of the CPU. The analyzer offers selective trace as well as performance analysis and statistic functions.

TRACE32 works with the highest variety of host interfaces. The communication link to the host is done by the printer port, a fibre optic interface or ethernet allowing a high-speed transfer.

TRACE32-ICE80 is also available as a compact 8-bit In-Circuit Emulator.


Link Doc
Download full document
ice80.pdf
( 286k)
Dim
Modules
Adaptions
Dimensions
Freq
Max. Operation Frequency
Volt
Operation Voltage
FAQ
Frequently Asked Questions
Order
Order
Information
Support
Technical Support
[www.zilog.com]  Zilog Home Page




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ICE 80 BASE


The ICE 80 probe is a high-performance emulation system for many derivates of the Z80 family. The change between different CPU types is done by changing the adapter board. The probe supports high-speed emulation and external bank systems. It runs together with the 8 bit controller ECC8 or the 32 bit controller ECU32.

Operating Modes

  • Reset Down
  • Reset Up
  • No Probe
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Max. Operation Frequency

  • 20 MHz

Operation with external or internal Clock

Internal Clock 0.75 to 25 MHz

Multitask Debugging

  • 1 foreground task
  • 1 background task
  • 10 tasks

Voltage and Clock Monitors for the Target System

Exception Control

  • Static Exception Setting
  • Reset
  • BUSREQ
  • Target Exception Control
  • Reset
  • Int0
  • Int1
  • Int2
  • NMI
  • Exception Trigger
  • Reset
  • Int0
  • Int1
  • Int2
  • NMI
  • Simulation
  • Exception Simulation
  • Reset
  • Int0
  • Int1
  • Int2
  • NMI
  • BUSREQ

Memory Banking (only Z80)

  • Off
  • Bank Probe
  • EPROM

Power Consumption

  • 6 W




Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 28-Jan-2016