In-Circuit Emulator for MC6833X The embedded tools company
Features
ICE 68330 Base
TPU Debugger
 home Products ICE In-Circuit Emulator In-Circuit Emulator for MC6833X


In-Circuit Emulator for MC6833X

Picture

 
33 MHz zero-waitstate emulation
 
17 MHz FastTerm emulation
 
3.3V/5V support
 
Trace on show-cycles
 
Premapper for 32 bit emulation
 
Address rebuild system
 
Port E replacement
 
FLASH support
 
TPU debugger
 
On-Circuit emulation with clip-over adapter
 
Interface with all compilers
 
C++ support
 
CASE tools interface
 
RTOS support
 
Windows9x, NT and Motif interface
 
Support for

MC68330, MC68331, MC68332, MC68334, MC68336, MC68338, MC68340, MC68341, MC68376, MC68F333, MC68HC16X1, MC68HC16Y1, MC68HC16Z, MC68HC916Y1

 


The TRACE32-ICE68330 supports most members of the 68330- and 68HC16-family from Motorola. The systems modular and open technology allows the fast integration of new chip designs.

A software compatible BDM debugger is also available, as well as several evaluation boards.


Doc
Download full document
ice68330.pdf
(592k)		 Dim
Modules
Adaptions
Dimensions		 Freq
Max. Operation Frequency		 Volt
Operation Voltage		 Faq
Frequently Asked Questions		 Order
Order
Information		 Support
Technical Support





TOP       ICE 68330 Base

Operating Modes

  • Reset Down
  • Reset Up
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Dual-Port Access

  • Request
  • Clock steal
  • Denied
  • Halt

Internal Clocks

  • VCO
  • 2.5/5/10 MHz
  • 32 KHz
  • VCO/100
  • Clocksteal

System Clock

  • Max. operation frequency 33.0 MHz
  • Operation with external or internal clock
  • Internal clock (EXTAL) 0.75 to 35 MHz

Wait System

  • Additional wait cycles (1-15) can be specified
  • Up to 250 wait cycles (4K blocks globally and bytewise)

Voltage and Clock Monitors for the Target System

Emulation System uses serial Debug Interface

  • Hardware based protocoll generator for max. debug speed
  • 10 MHz max. transfer speed

DMA Modes

  • Trace
  • Transparent

Exception Control

  • Static Exception Simulation
  • CPU Reset
  • Peripheral Reset
  • HALT
  • Bus Request
  • Bus Error
  • Exception Trigger
  • RESET
  • CPU Reset
  • HALT
  • Bus Request
  • Bus Error
  • Simulation
  • Exception Simulation
  • Reripheral Reset
  • CPU Reset
  • HALT
  • Bus Request

24 Additional Trace Channels

Full 32 Bit Address Mapping with Premapper

Global Breakpoints

Socket for GAL

  • ADDR to CS generation
  • CS to ADDR generation

Switch for Address and FC Lines

Reset Configuration by Software

Power Consumption

  • 10 W
TOP       TPU Debugger



TPU Debugger

Features

  • Fully support of TPU
  • Step and Go commands
  • Qualified breakpoints
  • Symbolic list
  • Register display




Navigation
Copyright © 2002 Lauterbach Datentechnik GmbH, Fichtenstr. 27, D-85649 Hofolding, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice.
Last generated/modified: Jun-3-2002