In-Circuit Emulator for MC68000 and MC6830X


The embedded tools company
ICE 68300 Base


Picture
  Highlights
Support for all family members
33 MHz no-waitstate emulation
3.3V and 5V support
Support for single and dual-chip emulation mode
Address reconstruction unit
On-Circuit emulation with clip-over adapter
Interface with all compilers
C++ support
CASE tools interface
RTOS support
Windows9x, NT and Motif interface
Support for KELVIN, MC68000, MC68008, MC68010, MC68302, MC68306, MC68307, MC68308, MC68328, MC68EC000, MC68EN302, MC68HC000, MC68HC001, MC68HC008, MC68HC010, MC68LC302, MC68LC302_3.3V, MC68PM302, MC68PM302_3.3V, MC68SEC000, TMP68301, TMP68303
 
  Introduction
The TRACE32-ICE68300 supports all members of the 68000/683xx-family from Freescale and some members of 683xx-family from Toshiba. The system is designed for bondout and non-bondout controllers. Its modular and open technology allows the fast integration of new chip designs.

A software compatible ROM Monitor is also available.

TRACE32 works with the highest variety of host interfaces. The communication link to the host is done by the printer port, a fibre optic interface or ethernet allowing a high-speed transfer.


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Max. Operation Frequency
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Operation Voltage
FAQ
Frequently Asked Questions
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ICE 68300 Base


Operating Modes

  • Reset Down
  • Reset Up
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Dual-Port Access

  • No Delay
  • Request
  • Denied
  • Halt

Max. Operation Frequency 25 (33) MHz

Operation with external or internal clock

Internal Clock 0.75 to 35 MHz

Multitask Debugging

  • 10 tasks
  • 1 foreground task
  • 1 background Ttask

Wait System

  • Additional wait cycles (1-15) can be specified
  • Up to 250 wait cycles (4K blocks globally and bytewise in 64K area)

Voltage and Clock Monitors for the Target System

Separate Breakpoint System for all TRAPS

Single Cycle Operation (WAIT or BR Modes)

Emulation does not use any Memory or TRAPS

Exception Control

  • Static exception setting
  • CPU Reset
  • Peripheral Reset
  • Halt
  • Bus Request
  • Target exception control
  • Reset
  • Halt
  • Bus Request
  • Bus Error
  • Auto Vector
  • NMI
  • Exception Trigger
  • Reset
  • CPU Reset
  • Halt
  • Bus Request
  • Bus Error
  • Simulation
  • All TRAPs
  • Exception Simulation
  • Peripheral Reset
  • CPU Reset
  • Halt
  • Bus Request
  • Bus Error
  • Rerun

Interrupt Simulation

  • Level-7-Interrupt
  • All TRAPs

Power Consumption

  • 10 W




Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 28-Jan-2016