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Emulator |
Operating Modes
- Reset Down
- Reset Up
- No Probe
- Alone Internal
- Alone External
- Emulation Internal
- Emulation External
Dual-Port Access
Clock System
- Max. operation frequency 20 MHz
- Operation with external or internal clock
- Internal clock 0.75 to 25 MHz
Supported DMA Modes
- External memory to port
- Memory to memory
- Internal memory to port
Multitask Debugging
- 10 tasks
- 1 foreground task
- 1 background task
Wait System
- Additional wait cycles (1-15) can be specified
- Up to 250 wait cycles (4K blocks globally and bytewise in 64K area)
Voltage and Clock Monitors for the Target System
Separate Breakpoint System for all TRAPs
Single Cycle Operation (WAIT or BR modes)
Emulation does not use any Memory or TRAPs
Exception Control
- Static Exception Setting
- CPU Reset
- Peripheral Reset
- Halt
- Bus Request
- Target Exception Control
- Reset
- Halt
- Bus Request
- Bus Error
- Auto Vector
- NMI
- Int1,2
- IN2,4,5
- Req1,2
- Exception Trigger
- Reset
- CPU Reset
- Halt
- Bus Request
- Bus Error
- Simulation
- All TRAPs
Exception Simulation
- Peripheral Reset
- CPU Reset
- Halt
- Bus Request
- Bus Error
- Rerun
Interrupt Simulation
- Level-7-Interrupt
- All TRAPs
Trace Information (24 additional channels)
- Physical address
- Logical address
- Data
- Cycle type (opfetch, DMA, ...)
- Bus width
- Wait
- Bus Request
- Bus Grant
- Bus Grant Acknoledge
- Bus Error
- Halt
- DMA
- Reset
- Auto Vector
- Int1..2
- IN2,4,5
- NMI
- Done
- Peripheral Interrupt Acknoledge
- Timer 1
- Timer 2
- CTS
- RTS
- DTC
Power Consumption
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