In-Circuit Emulator for MC68040/60

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ICE 68040 Base

In-Circuit Emulator for MC68040/60
Support for 3.3 and 5 Volt derivatives
Interface with all compilers
C++ support
MMU Support
FPU Support
Hidden Wait System
Dual ported memory
Support for Companion Mode MC68360
CASE tools interface
RTOS support
Windows9x, NT and Motif interface
Support for MC68040, MC68040V, MC68060, MC68EC040, MC68EC040V, MC68EC060, MC68LC040, MC68LC060
TRACE32-ICE68040 supports MC68040/MC68040V up to 40 MHz bus speed and MC68060 up to 40 MHz in half-speed bus mode and up to 45 MHz in full-speed bus mode. The LC and EC versions of both CPUs are also supported.

The modular and open technology of the system allows the fast integration of new chip designs.

TRACE32-ICE is a state of the art In-Circuit Emulator, which offers unlimited hardware breakpoints and up to 16MByte dual-ported emulation memory. The real-time trace and trigger work up to the max. speed of the CPU. The analyzer offers selective trace as well as performance analysis and statistic functions.

TRACE32 works with the highest variety of host interfaces. The communication link to the host is done by the printer port, a fibre optic interface or ethernet allowing a high-speed transfer.

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Max. Operation Frequency
Operation Voltage
Technical Support
[]  Freescale 68040 Site
[]  Freescale 68060 Site


ICE 68040 Base

Max. Frequency

  • 20 MHz No wait (25ns SRAM)
  • 25 MHz 1 wait
  • 33 MHz 2 wait
  • 40 MHz 3 wait

Operating Modes

  • Reset Down
  • Reset Up
  • No Probe
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Dual-Port Access

  • Request
  • Denied

Operation with external or internal Clock

Internal Clock 0.75 to 35 MHz

Multitask Debugging

  • 10 tasks
  • 1 foreground task
  • 1 background task

Wait System

  • Additional wait cycles (1-15) can be specified
  • Up to 250 wait cycles (4K blocks globally and bytewise in 64K area)

Voltage and Clock Monitors for the Target System

TRAPs used for Emulation

  • BPT0..7 selectable

Exception Control

  • Static Exception Setting
  • CPU Reset
  • Peripheral Reset
  • Bus Request
  • Target Exception Control
  • Reset
  • Bus Request
  • Bus Error
  • Auto Vector
  • NMI
  • INT1...INT7
  • Exception Trigger
  • Reset
  • CPU Reset
  • Bus Request
  • Bus Error
  • Simulation
  • Exception Simulation
  • Peripheral Reset
  • CPU Reset
  • Bus Request

Interrupt Simulation

  • Level-1..7-Interrupt
  • All Vectors

FPU Support

MMU Support

  • Display of Register
  • Display of Translation Tables
  • Debugging with logical Addresses
  • Separate logical Memory Spaces for Multitask Environments

32 Additional Trace Channels

Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 13-Dec-2016