In-Circuit Emulator for MC68020/30


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ICE 68020 Base


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  Highlights
33 MHz no-waitstate emulation
MMU support
FPU support
Support for companion mode MC68360
Interface with all compilers
C++ support
CASE tools interface
RTOS support
Windows9x, NT and Motif interface
Support for MC68020, MC68030, MC68EC020, MC68EC030
 
  Introduction
The ICE68020 emulator module supports the MC68020 and MC68030 processors from Freescale. The EC versions are supported as well.

The software has direct access to MMU and FPU functions.

A software compatible ROM monitor is available.

TRACE32-ICE is a state of the art In-Circuit Emulator, which offers unlimited hardware breakpoints and up to 16MByte dual-ported emulation memory. The real-time trace and trigger work up to the max. speed of the CPU. The analyzer offers selective trace as well as performance analysis and statistic functions.

TRACE32 works with the highest variety of host interfaces. The communication link to the host is done by the printer port, a fibre optic interface or ethernet allowing a high-speed transfer.


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ICE 68020 Base


Supported CPUs

  • MC68020
  • MC68EC020
  • MC68030
  • MC68EC030

Operating Modes

  • Reset Down
  • Reset Up
  • No Probe
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Dual-Port Access

  • Request
  • Denied

Max. Operation Frequency

  • 20 MHz 0 wait state 70ns SA120
  • 25 MHz 1 wait state 70ns SA120
  • 33 MHz 2 wait state 70ns SA120
  • 25 MHz 0 wait state 25ns HA120
  • 33 MHz 1 wait state 25ns HA120

Operation with External or Internal Clock

Internal Clock 0.75 to 35 MHz

Multitask Debugging

  • 10 tasks
  • 1 foreground task
  • 1 background task

Wait System

  • Additional wait cycles (1-15) can be specified
  • Up to 250 wait cycles (4K blocks globally and bytewise in 64K area)

Voltage and Clock Monitors for the Target System

Emulation does not use any Memory

TRAPs used for Emulation

  • BPT0,2,4,7 selectable

Exception Control

  • Static Exception Setting
  • CPU Reset
  • Peripheral Reset
  • Halt
  • Bus Request
  • Target Exception Control
  • Reset
  • Halt
  • Bus Request
  • Bus Error
  • Auto Vector
  • NMI
  • INT
  • Exception Trigger
  • Reset
  • CPU Reset
  • Halt
  • Bus Request
  • Bus Error
  • Simulation
  • Exception Simulation
  • Peripheral Reset
  • CPU Reset
  • Halt
  • Bus Request

Interrupt Simulation

  • Level-7-Interrupt
  • All Vectors

FPU + MMU Support

32 Additional Trace Channels

Limitations

  • No Burst Mode (68030)




Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 28-Jan-2016