In-Circuit Emulator for 80196 The embedded tools company
Features
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 home Products ICE In-Circuit Emulator In-Circuit Emulator for 80196


In-Circuit Emulator for 80196

Picture

 
Bondout support
 
Works with Intel, Tasking and IAR Compilers
 
C++ support
 
Dual ported memory
 
Banking support for 256 banks
 
Supports memory split for program and data
 
CASE tools interface
 
RTOS support
 
Software compatible ROM Monitor
 
Windows95, NT and X windows interface
 
Support for

8XC196CA, 8XC196CB, 8XC196EA, 8XC196JQ, 8XC196JR, 8XC196JT, 8XC196JV, 8XC196KQ, 8XC196KR, 8XC196KS, 8XC196KT, 8XC196NQ, 8XC196NT

 


The TRACE32-ICE196 supports bondout microcontroller from Intel. Its modular and open technology allows the fast integration of new chip designs.

A software compatible SDU Debugger is available for the 196EA. All other derivatives are supported by a ROM Monitor.

TRACE32 works with the highest variety of host interfaces. The communication link to the host is done by the printer port, a fibre optic interface or ethernet allowing a high-speed transfer.


Link Doc
Download full document
ice196.pdf
(373k)		 Dim
Modules
Adaptions
Dimensions		 Freq
Max. Operation Frequency		 Volt
Operation Voltage		 Order
Order
Information		 Support
Technical Support
[developer.intel.com]  Intel 196 Site





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Operating Modes

  • Reset Down
  • Reset Up
  • No Probe
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Dual-Port Access

  • No Delay
  • EGAP
  • Denied

Max. Operation Frequency

  • 20 MHz

Operation with external or internal Clock

Internal Clock 0.75 to 25 MHz

Multitask Debugging

  • 1 foreground task
  • 1 background task

Wait System

  • Additional wait cycles (1-15) may be specified
  • Up to 250 wait cycles (4K blocks globally and bytewise)

Banking support

  • Up to 256 Banks of up to 16MByte size

Voltage and Clock Monitors for the Target System

Exception Control

  • Static Exception Setting
  • CPURESET
  • PERRESET
  • Target Exception Control
  • CPURESET
  • PERRESET
  • NMI
  • Exception Trigger
  • INT
  • TRAP
  • UNIMP
  • Simulation
  • Exception Simulation
  • CPURESET
  • NMI




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Copyright © 2002 Lauterbach Datentechnik GmbH, Fichtenstr. 27, D-85649 Hofolding, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice.
Last generated/modified: Jun-3-2002