In-Circuit Emulator for C166 / ST10
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Features


Picture
  Highlights
Full support for standard, VECON and GOLD
Full support for KEIL, TASKING and GNU compilers
Bondout and non-Bondout Probes
25 MHz no-wait-state operation
Dual-port access for ROM and external bus
Trace on internal and local variables
Selective trace on registers, peripherals and local variables
Trigger on internal register access, bit, byte, and word variables
Mixed trace on external and BONDOUT busses
Clip-Over, Solder-On and YAMAICHI adapters
Support of all derivatives, also non-public versions
Support for
 C161CI, C161CS, C161JI, C161K, C161O, C161PI, C161RI, C161S, C161SI, C161V, C161XX, C163, C163-16F, C163-24D, C164CH, C164CI, C164CL, C165, C167, C167C, C167CR, C167CS, C167CW, C167SR, PMB2705GOLD, PMB2706GOLD, PMB2800HIGOLD, PMB2800HIGOLDV4, SAB80C166, SAB83C166, SAB88C166, ST10F163, ST10F166, ST10F167, ST10F168, ST10R163, ST10R165
 
  Introduction
The ICE-166 emulator module support bondout and non-bondout derivatives of the C166 family. All features of the BONDOUT chips are supported, trigger and selective trace is possible on internal addresses and data, on registers and on peripheral accesses. 160 extra trace channels are used to trace all BONDOUT signals. The ROM and FLASH memory is emulated by an extra emulation system with separate breakpoints and execution flags for code coverage. The emulator can simulate bootstrap sequences and FLASH operation.


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ice166.pdf
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[www.infineon.com]  Infineon C166 Product Page
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Features

Operating Modes

  • Reset Down
  • Reset Up
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Dual-Port Access for external Bus

  • GAP
  • NoGAP
  • NOP (BONDOUT only)
  • Denied

Dual-Port Access for internal Bus

  • Always possible with no speed limitation

ROM Emulation

  • 256K ROM emulation
  • No speed limit
  • Fully dual-ported
  • Separate 256K*8 BREAK memory

Flag Memory

  • Additional flag memory for ROM
  • Separate flags for OPFETCH and ROMDATA

Trace Extension

  • 128 channels for BONDOUT busses
  • Instruction execution address
  • Operand read address
  • Operand write address
  • Operand data
  • Control lines
  • Instruction code

Trace Operation

  • Internal CPU cycles (BONDOUT only)
  • External bus cycles
  • Mixed trace (BONDOUT only)

Code Sequences

  • Qualifies internal busses for breakpoint system

Breakpoints and Analyzer Qualifiers

  • 2 operand data (OD, ODX)
  • 2 bit write
  • 2 operand write address
  • 2 operand read address

Execution Breakpoints

  • 256K execution breakpoints

HLL Debugging

  • Full support in real-time
  • ROM and external busses
  • Break-before-line operation
  • HLL single step in real-time
  • Trigger and trace on local variables
  • Trigger on bit variables

Operation with external or internal Clock

  • 1..35 MHz internal clock

Multitask Debugging

  • 1 foreground task
  • 1 background task

Wait System

  • Additional wait cycles (1-15) may be specified
  • Up to 250 wait cycles (4K blocks global and bytewise)

Voltage and Clock Monitors for the Target System

On-Line Display for SYSCON and BUSCON

Exception Control

  • Static Exception Setting
  • RSTIN
  • Target Exception Control
  • RSTIN
  • NMI
  • Exception Trigger
  • RSTOUT
  • RSTIN
  • PWRDOWN
  • IDLE
  • TRAP
  • PEC

Port Analyzer

  • Slot for Port Analyzer

On-Circuit Emulation

  • Support for Clip-Over adapters




Copyright © 2002 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice.
Last generated/modified: 3-Jun-2002