In-Circuit Emulator for 68HC11


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ICE 11 BASE


Picture
  Highlights
Modular design for up to 6 MHz
Support for 5V and 3.3V
Banking and MMU support
Support for single chip and expanded mode
On chip EEPROM access
Support for test modes
Trace and trigger on internal accesses
Bootloader support
Support for all compilers
Available as cost effective TRACE32-COMPACT
Windows9x, NT and X windows interface
Support for MC68HC11A, MC68HC11C, MC68HC11D, MC68HC11E, MC68HC11F, MC68HC11G, MC68HC11K, MC68HC11KA, MC68HC11KW, MC68HC11N, MC68HC11P, MC68HC11PH, MC68HC711D, MC68HC711E, MC68HC711K, MC68HC711KA, MC68HC711P, MC68HC811E
 
  Introduction
The ICE-11 probe is a high-performance emulation system for many derivates of the 68HC11 family including the CPUs with MMU. The change between different CPU types is done by changing the adapter board.

The probe supports high-speed emulation. The CPU can be emulated in single chip or expanded mode. The test mode is available for both modes. The emulator can support up to 256 banks. Internal access to RAM or peripherals can be traced and triggered.

As internal address bus is 20 bit the K4 version may be supported with or without MMU.

TRACE32 for the 68HC11 family is available as an 8-bit compact solutions and as 32-bit emulation system.


Link Doc
Download full document
ice11.pdf
( 287k)
Dim
Modules
Adaptions
Dimensions
Freq
Max. Operation Frequency
Volt
Operation Voltage
FAQ
Frequently Asked Questions
Order
Order
Information
Support
Technical Support
[www.freescale.com]  Freescale Microcontroller Site


Demo Software for Download



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ICE 11 BASE


Operating Modes

  • Reset Down
  • Reset Up
  • No Probe
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Max. Operation Frequency

  • 6 MHz (24 MHz clock)

Emulation Modes

  • Single-Chip
  • Expanded
  • Test
  • Single Test

Internal Clock 0.75 to 25 MHz

Multitask Debugging

  • 1 foreground task
  • 1 background task

Trace Control

  • TraceReset
  • TraceWait
  • TraceAll
By default no prefetch or idle cycles are traced

Voltage and Clock Monitors for the Target System

  • Clock monitor may be swichted off

Exception Control

  • Static Exception Setting
  • Reset
  • Target Exception Control
  • Reset
  • IRQ
  • XIRQ
  • Exception Trigger
  • Reset
  • IRQ
  • XIRQ
  • Simulation
  • Exception Simulation
  • Reset
  • IRQ
  • XIRQ

Memory Banking

  • Off
  • Probe (external)
  • EPROM (internal)
  • MMU support for K4 version

EEPROM Support

  • EEPROM may be loaded or erased directly (monitor based EEPROM write function)

Direct Access to Register Area

Real-Time Cycle Sequencing

  • Functional stamps on all cycles
  • No trace of prefetch or idle cycles
  • Internal/external stamp
  • Stack/data stamp
  • Normal/exception cycle stamp
  • Wait cycle stamp
  • No trigger on prefetch cycles
  • No flag setting on prefetch cycles
  • Protection data/programm

Trace no Idle or Prefetch

Trace all Cycles

Power Consumption

  • 6 W




Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 28-Jan-2016