ICE In-Circuit Emulator The embedded tools company


ICE In-Circuit Emulator

Picture

 
Timing Analyzer
 
Emulation Memory
 
Memory Banking
 
ICE Module
 
State and Performance Analyzer
 
Emulation Controller
 
System Controller
 


TRACE32-ICE is a state of the art In-Circuit Emulator, which offers unlimited hardware breakpoints and up to 16MByte dual-ported emulation memory. The real-time trace and trigger work up to the max. speed of the CPU. The analyzer offers selective trace as well as performance analysis and statistic functions.

The system offers an interface to all programming languages for most compilers and a multitask debugger for a wide range of RTOS. TRACE32 works with the highest variety of host interfaces. The communication link to the host is done by the printer port, a fibre optic interface or ethernet allowing a high speed transfer.

TRACE32-ICE is universal In-Circuit Emulator and supports a wide range of 8- to 32-bit microprocessors and microcontrollers. Its modulare architecture allows:

1. to adapt the emulator to your project requirements

2. to integrate the emulator in any project environment

3. to adapt the emulator easily to different CPUs

4. to support new CPUs in record time


Link Doc
Download full document
ice.pdf
(101k)
Faq
Frequently Asked Questions
Order
Order
Information

Demo Software for Download





TOP       Basic Concept











TOP       Modules



     Timing and Protocol Analyzer

Timing analyzer up to 200 MHz
Time correlation with state analyzer
Selective trace controlled by state analyzer
State analyzer mode
16 channel pattern generator
2 channel serial line tester

     Port Analyzer

64 Channels
10 MHz Timing
Slave Operation to State Analyzer
Time Stamp
List and Timing Display




     ICExxx Emulation Probes

Emulation
Exception Simulation
Exception Control


     State and Performance Analyzer

120 Channel Trace
High-Level Trigger Unit
25 ns Time Stamp
Master-Slave Trigger
Selective Trace
Statistic Display
Timing Display
Performance Analyzer
Coverage Analysis






     Emulation Memory Modules

SRAM Emulation Memory
DRAM Emulation Memory
Up to 16 MByte

     SDIL Emulation Memory

512K+512K M or 2+2 M Emulation+Breakpoint Memory
     Shadow Memory Module

Dual-Port Read Access with no Restrictions
Dynamic Mapping
4 Blocks with 64K
RAM Coverage Test
Recommended for ICE-166, ICE-196, ICE-ARM, ICE-H8



     32 Bit Emulation Controller

Universal Emulation Controller
8 .. 32 Bit Support
Mapper
Trigger System
Banking Support
Code Coverage
Universal Counter
Pulse Generator
VCO



     32 Bit Emulation Compact Controller

Universal Emulation Controller
8 .. 32 Bit Support
Mapper
Trigger System
Banking Support
Code Coverage
Universal Counter
Pulse Generator
VCO
Trace Analyzer
Performance Analyer



     8 Bit Emulation Compact Controller

Universal Emulation Controller
Support for all 8 Bit Probes
Mapper
Trigger System
Banking Support
Code Coverage
Universal Counter
Pulse Generator
VCO
Trace Analyzer
Performance Analyzer

     System Controller 32 Bit

Up to 50 MIPS
Max. 64 MByte Memory
Parallel Interface
Ethernet Interface
USB Interface
Master-Slave Synchronisation


TOP       Configuration Examples





Compact Emulator for 8 Bit

  • SCU32
  • ECC8
  • ICExxx
 




Compact Emulator for 32 Bit

  • SCU32
  • ECC32
  • SDIL
  • ICExxx
 





Compact Emulator for 32 Bit with Large Emulation Memory

  • SCU32
  • ECC32
  • SRAM
  • ICExxx
 





Emulator for 32 Bit with full Analyzer Features

  • SCU32
  • ECU32
  • SDIL
  • HA120
  • ICExxx
 






Emulator for 32 Bit with full Analyzer Features and Large Emulation Memory

  • SCU32
  • ECU32
  • SRAM
  • HA120
  • ICExxx
 






Emulator for 32 Bit with addtitional Timing and Port Analyzer

  • SCU32
  • ECU32
  • SDIL
  • HA120
  • ICExxx
  • PA64
  • TA32
TOP       Related WWW Sites





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Copyright © 2009 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice.
Last generated/modified: Jul-1-2009