State and Performance Analyzer

State Analyzer

120 Trace Channels

• 24 bit address
• 4 bit address range
• 16 bit data
• 8 bit state signals
• 4 bit bank access signals
• 24 bit universal channels
• 3 bit markers
• 3 bit 8 trigger levels
• 16 bit external trigger inputs
• 1 bit DMA access
• 4 bit task no.
• 8 bit reserved
• 5 bit internal

High-Speed 50ns Cycle Time

Large Trace Depth (32 KFrames)

Trace Memory Depth programmable from 0.1 K to 32 K

Two Operating Modes - FIFO and STACK

Freely defined Markers can also be recorded to highlight specific Routines

Time Correlation available with Logic Analyzer

Internal Expansion Capability

For emulator modules which need more than 24 bits of address or more than 16 bits of data, the necessary extra bits are built into the emulator module itself.

External Trigger Inputs

• 2 inputs each with 8 channels
• 2 trigger qualifiers for each trigger level and channel group
• Each channel group can be assigned 2 trigger events for each level, definable using boolean formulae
• Static levels of the trigger inputs can be read at any time
• Free format definition of external trigger events
• Connection from digital test pods

Free Format Definition of Data Events

Data events can be specified with constants, masks, range or boolean formulae.

Hex and Mnemonic Display of Trace Data

Configurable Display

• Dissassembly or Hll
• Special Channels
• Ascii/Hex/Decimal/Bin
• Suppress Prefetching
• Dequeued DIsassembly

Graphic Display

• Real time display
• Tracking to List Windows

Graphical Data Display

• Show A/D Conversion
• Visualize Program Flow

Complex Search and Compare Functions

Save and Reload of Trace Data

PC Display on Real-Time Emulation

5 Trigger Outputs

• 3 freely programmable outputs
• Cycle signal
• RUN signal
• BNC connector for oscilloscope trigger
  
  

Trigger Unit

Programmed via a special Window

The programming of this complex trigger unit is done in an assembler-like language for maximum flexibility. Using this language, the programming of very complex trigger sequences or operations can be defined.

Fast programming via window

The most program settings can be made by menu based fast programming window

Symbolic Operation

All output operators and input variables can be input in symbolic form. The target program symbols can also be used.

Free Format Definition of Data, Address and Trigger Events

Time and Event Measurements with up to 3 Counters

There are 3 40 bit counters available for event measurement or event triggering. All counters are re-triggerable and can be evaluated as a part of an expression in the trigger sequences. Each counter can be programmed as a timer for timing measurements or an event counter.

3 Universal Counters - 40 Bit

• Event count 1 to 1.1 E + 12
• Cycles 1 to 1.1 E + 12
• Time 100ns to 1.3 days
• Retriggerable
• Selective release
• Trigger event when counter is zero
• Definition of time and event windows

All Counters can be read `on the fly'

Trigger Monitor

A display of the count values, the trigger values, the trigger levels and the trigger flags is available in the trigger monitor window.

Trigger Flags

Independent of the trigger levels, there are 3 freely programmable trigger flags. These flags can be read during triggering and can be used as input variables by the trigger sequencer.

48 input variables

• READ, USERDATA, OPFETCH CPU status
• PROGBREAK program breakpoint
• LINE high-level line number
• SPOT spot point
• READBREAK data read breakpoint
• WRITEBREAK data write breakpoint
• A,B,C address points
• TRIGG0,TRIGG1 bus trigger events
• TRIGGER trigger events (3 per level)
• NMI, RESET trigger events from the CPU
• FULL trace memory full
• READ, WRITTEN read or write flag
• MAIN main process
• BREAK break event
• TIMEOUT timeout signal
• SYNCH synchronous trigger
• ASYNCH asychronous trigger
• ECOUNT universal counter zero
• DLATCH task monitor

48 Output Functions

• TRACE trace release
• TRACEON trace memory on
• TRACEOFF trace memory off
• GOTO change trigger level
• FLAGON flag on
• FLAGOFF flag off
• FLAGTOGGLE flag TOGGLE
• TRIGG0,TRIGG1 triggering via ICEBUS
• MARKERA...MARKERC markers in the TRACE memory
• BREAK trigger emulator
• STOP break Emulator
• SPOT spotpoint emulator
• EXCEPTION trigger exception generator
• RESTART reload counter
• ENABLE enable counter release
• OUT0.....OUT2 trigger outputs (test probe)
• DLATCH task monitor
• LEVEL level control

Time Stamp

Time Stamp

The Time Stamp Unit tags each trace record with a time value. These values are absolute and sychronised with all the other time values within the TRACE32 system.

• Recording depth max. 32K
• 48 time stamp recording channels
• Resolution 25ns
• Relative channel precision 25ns
• Relative instrument precision 25ns
• Maximum measuring time 1.3 days

Statistic Functions

Function Analysis

• Min. and max. time
• Passes
• Include and exclude time

Link Analysis

• Callers
• Min. and max. times
• Calls

Function Nesting

• Shows function call hierarchy
• Time suspend in subroutines
  
  
  
  

Function Timechart

• View critical program
  paths
• Documentation

Duration

• Execution time
• Response time

Distance

• Time between samples

Distribution

• Interface analysis
• Interrupt analysis
• System state analysis
• Statistical analysis

Distribution Timecharts

• Timing of system states

Coverage Analysis

Controlled by software, the captured address ranges can be collected.

• Display of captured addresse
• Display of captured functions

Performance Analysis

The statistic unit measures independently from the trace memory, the run time of specific modules of the program. Using this, the average execution time, the average execution frequency and the absolute number of calls to the entry point of a routine can be measured. Up to 63 routines can be monitored in this way.

• Resolution 1 us
• Sample rate 100 us to 10s selectable
• Separate analysis of program and data accesses
• Sampling window definable through trigger unit

Modes

• Program address
• Access
• Level
• Flags
• Automatic programming
• Scanning

Selection of Address Ranges

• Modules
• Functions
• Address ranges
• Automatic Modes
• Scanning Modes

Display

• Duration
• Ratio
• Average
• Passes
• Total Time

Configurable Display

• Select items
• Graphical or Numerical

Detailed view

Hypertrace

The optimal Hypertrace Unit improves the address recording capability of the high-speed state analyzer HA120 either about 1 MFrame or 4 MFrame. This can be used for a long-time trace ( program flow and function nesting monitoring ) and for a powerful prestore analysis.

Hypertrace Memory

• 1 MFrame/4 MFrame by 40 bit
• Min. cylcle time 110ns

Long-Time Trace

• Program flow recording with various display window functions
• Function nesting monitoring for long-time using the conditions of the trace memory statistic.

Improved Prestore Function

• Records up to 32/64 prestore cycle for each usual record in the HA120 trace memory.

Probes

CIN8

CREF8

COUT8

Clip Set