FIRE Emulator for ST10


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FIRE Emulator for ST10, ST10F167, ST10F168, ST10F269, ST10F172, ST10F272
  Highlights
Full support for ST10 family
Full support for KEIL, TASKING, COSMIC and GNU compilers
50 MHz no-wait-state operation
Dual-port access for ROM and external bus
Dual-port access for XRAM
Shadow-RAM for IRAM and XRAM
FLASH Programming Support
Trace on internal and local variables
Selective trace on registers, peripherals and local variables
Trigger on internal register access, bit, byte, and word variables
Trace on external and BONDOUT busses, bus and clock cycle trace
Clip-Over, Solder-On and YAMAICHI adapters
Support for
 C165, C167, C167C, C167CR, C167CS, C167CW, C167SR, ST10F163, ST10F167, ST10F168, ST10F169, ST10F251, ST10F251M, ST10F252, ST10F252M, ST10F269, ST10F271, ST10F271B, ST10F271M, ST10F272, ST10F272B, ST10F272M, ST10F273, ST10F273M, ST10F275, ST10F276, ST10F280, ST10F293, ST10F296, ST10R163, ST10R165, ST10R167, ST10R172L, ST10R251, ST10R252, ST10R262, ST10R271, ST10R272, ST10R272L, XCORE
 
  Introduction
The FIRE-ST10 emulator module supports the whole ST10 family. All features of the BONDOUT chips are supported, trigger and selective trace is possible on internal addresses and data, on registers and on peripheral accesses. 128 extra trace channels are used to trace all BONDOUT signals. The ROM and FLASH memory is emulated by an extra emulation system with separate breakpoints and execution flags for code coverage. The emulator can simulate bootstrap sequences and FLASH operation.


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Demo Software for Download
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Features



The FIRE-ST10 Emulator consists ot 3 modules:


      ST10/C166 Bondout Trigger Module
      ST10 Bondout Module
      CPU Adapter
      
      Adapter (Clip-Over, Solder-On, AMP, YAMAICHI)
      

 
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Bondout Module




Operating Modes

  • Reset Down
  • Reset Up
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Operation Frequency

  • 50 MHz Zero-Waitstate FLASH Emulation
  • 40 MHz External Memory Emulation with Zero Wait States and Dualport Access

Dual-Port Access

  • Zero-Wait State Access for ROM/FLASH RAM
  • Zero-Wait State Access for External Emulation Memory
  • Zero-Wait State Access for XRAM
  • Injected access for all other areas and peripherals

ROM Emulation

  • 512K ROM/FLASH emulation
  • No speed limit
  • Fully dual-ported

Trace Operation

  • Bondout CPU Cycles
  • External BUS Cycles
  • Internal and External Cycles
  • Clock Trace

HLL Debugging




  • Full support in real-time
  • ROM and external busses
  • Break-before-line operation
  • HLL single step in real-time
  • Trigger and trace on local variables
  • Trigger and trace on bit variables

Operation with external or internal Clock

  • 1..150 MHz internal clock

Voltage and Clock Monitors for the Target System

Exception Control




  • Static Exception Setting
  • RSTIN
  • Target Exception Control
  • RSTIN
  • NMI
  • Exception Trigger
  • RSTOUT
  • RSTIN
  • PWRDOWN
  • IDLE
  • TRAP
  • PEC

Foreground Monitor Support

  • Support of Foreground Monitor Systems in FLASH and External Memory

JTAG

  • 20 MHz hardware-based TAP controller
  • More than 300 KByte/sec JTAG transfer speed

 
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Bondout Trigger Module


Bondout Trace with 128 Channels

  • 24 Bit Code Execution Address
  • 24 Bit Operand Read Address
  • 24 Bit Operand Write Address
  • 16 Bit Operand Data
  • 16 Bit Opcode
  • 24 Bit Control Signals

Hardware Dequeuing

  • Automatic Dequeeing of all Data and Control Signals
  • Simple Trigger and Selective Trace Control

Code Coverage for ROM and External Memory



  • 1 or 4 MByte, can be remapped to exery address within the full address range
  • Only Execution Cycles, no prefetches
  • Hardware-based C1 analysis possible

Data Read Access Flag System

  • 2 ranges with 1 or 4 MByte each, can be remapped to exery address within the full address range
  • 1 Byte resolution

Data Write Access Flag System

  • 2 ranges with 1 or 4 MByte each, can be remapped to exery address within the full address range
  • 1 Byte resolution

Code Breakpoint Memory

  • 4 breakpoint areas with 1 MByte each
  • Dynamic remap to every base address
  • 4 different breakpoints types can be defined
  • Every breakpoint can be qualified by data value, mask or pattern (local variable triggering)

Data Access Breakpoint Memory

  • 4 Breakpoint Areas with 1 MByte each
  • Dynamic remap to every base address
  • 4 different breakpoints types can be defined
  • Separate READ and WRITE breakpoints
  • Every breakpoint can be qualified by data value, mask or pattern

 
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CPU Adapters


Port Analyzer

  • Trace an all peripheral ports

XPER Emulation Socket



On-Circuit Emulation

  • Support for Clip-Over adapters
  • Power-Up Reset for Target CPU

Automatic Setup Configuration by Reading Reset Vectors

Support of Reset Vectors for Standalone Operation



 
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Port Analyzer


 
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IDE - Integrated Development Environment






Copyright © 2016 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 18-Oct-2016