FIRE Emulator for C166 Family The embedded tools company


FIRE Emulator for C166 Family

C161CI C161K C161O C161PI C161RI C161S C161SI C161V C161XX C163 C163-16F C163-24D C164CI C164CL C164CM C164SI C164SM C164SV C165 C167 C167C C167CR C167CS C167CW C167SR
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  Highlights
Full support for C167 family
Full support for KEIL, TASKING, COSMIC and GNU compilers
40 MHz no-wait-state operation
Dual-port access for ROM and external bus
Dual-port access for XRAM
Shadow-RAM for IRAM and XRAM
FLASH Programming Support
Hardware Dequeuing
Code Coverage
Trace on internal and local variables
Selective trace on registers, peripherals and local variables
Trigger on internal register access, bit, byte, and word variables
Trace on external and BONDOUT busses, bus and clock cycle trace
Clip-Over, Solder-On and YAMAICHI adapters
Support of all derivatives, also non-public versions
Compatible ROM Monitor
 
  Introduction
The FIRE-166 emulator module supports the whole C166 family. All features of the BONDOUT chips are supported, trigger and selective trace is possible on internal addresses and data, on registers and on peripheral accesses. 128 extra trace channels are used to trace all BONDOUT signals. The ROM and FLASH memory is emulated by an extra emulation system with separate breakpoints and execution flags for code coverage. The emulator can simulate bootstrap sequences and FLASH operation.


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[www.infineon.com]  Infineon C166 Product Page

Demo Software for Download



TOP       Introduction

The FIRE166 Emulator consists ot 3 modules:


      ST10/C166 Bondout Trigger Module
      C167E3 Bondout Module
      CPU Adapter
      
      Adapter (Clip-Over, Solder-On, AMP, YAMAICHI)
      

TOP       Bondout Module

Operating Modes




  • Reset Down
  • Reset Up
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Operation Frequency

  • 40 MHz Zero-Waitstate FLASH Emulation
  • 40 MHz External Memory Emulation with Zero Wait States and Dualport Access

Dual-Port Access

  • Zero-Wait State Access for ROM/FLASH RAM
  • Zero-Wait State Access for External Emulation Memory
  • Zero-Wait State Access for XRAM

ROM Emulation

  • 512K ROM/FLASH emulation
  • No speed limit
  • Fully dual-ported

Trace Operation

  • Bondout CPU Cycles (fully depipelined)
  • External BUS Cycles
  • Internal and External Cycles
  • Clock Trace

HLL Debugging




  • Full support in real-time
  • ROM and external busses
  • Break-before-line operation
  • HLL single step in real-time
  • Trigger and trace on local variables
  • Trigger and trace on bit variables

Operation with external or internal Clock

  • 1..150 MHz internal clock

Voltage and Clock Monitors for the Target System

Exception Control




  • Static Exception Setting
  • RSTIN
  • Target Exception Control
  • RSTIN
  • NMI
  • Exception Trigger
  • RSTOUT
  • RSTIN
  • PWRDOWN
  • IDLE
  • TRAP
  • PEC

Foreground Monitor Support

  • Support of Foreground Monitor Systems in FLASH and External Memory

TOP       Bondout Trigger and Trace Module




Bondout Trace with 128 Channels

  • 24 Bit Code Execution Address
  • 24 Bit Operand Read Address
  • 24 Bit Operand Write Address
  • 16 Bit Operand Data
  • 16 Bit Opcode
  • 24 Bit Control Signals

Hardware Dequeuing

  • Automatic Dequeeing of all Data and Control Signals
  • Simple Trigger and Selective Trace Control

Code Coverage for ROM and External Memory




  • Two 1 or 4 MByte areas, can be remapped to exery address within the full address range
  • Only Execution Cycles, no prefetches
  • Hardware-based C1 analysis possible

Data Read Access Flag System

  • 2 ranges with 1 or 4 MByte each, can be remapped to exery address within the full address range
  • 1 Byte resolution

Data Write Access Flag System

  • 2 ranges with 1 or 4 MByte each, can be remapped to exery address within the full address range
  • 1 Byte resolution

Code Breakpoint Memory

  • 4 breakpoint areas with 1 MByte each
  • Dynamic remap to every base address
  • 4 different breakpoints types can be defined
  • Every breakpoint can be qualified by data value, mask or pattern (local variable triggering)

Data Access Breakpoint Memory

  • 4 Breakpoint Areas with 1 MByte each
  • Dynamic remap to every base address
  • 4 different breakpoints types can be defined
  • Separate READ and WRITE breakpoints
  • Byte aligned breakpoints
  • Every breakpoint can be qualified by data value, mask or pattern

Shadow Memory

  • 1 MByte Shadow Memory
  • Can be remapped
  • Tracking of external, IRAM and XRAM variables on the fly

TOP       CPU Adapters

Port Analyzer

  • Trace an all peripheral ports

XPER Emulation Socket




On-Circuit Emulation

  • Support for Clip-Over adapters
  • Power-Up Reset for Target CPU

Automatic Setup Configuration by Reading Reset Vectors

Support of Reset Vectors for Standalone Operation

TOP       Compatible ROM Monitor

C166 Monitor



  • Compatible with Emulator
  • Support for C,C++ and ASM
  • Communication via Eprom Simulator
  • Communication via RS232 or customized .DLL link
  • Support for Keil, Tasking and GNU
  • Monitor Code with Source
  • Monitor Code Royalty Free


TOP       Port Analyzer

TOP       IDE - Integrated Development Environment

ASM Debugger
  • Supports almost all file formats
  • Assembler source-level debugging
  • Advanced memory display
  • Inline assembler
  • Memory tests
  • Customizable windows
  • Peripheral windows
  • Terminal window
  • Semi-hosting
  • Flash programming
  • Full support for peripherals
High-Level-Language Debugging
  • Supports multiple languages
  • Full support for C++
  • Integrated into TRACE32 environment
  • Supports most compilers and hosts
  • Same user interface on different hosts
  • High speed download
  • Debugs optimized code
  • Display of function nesting
  • Display of linked lists
  • Powerful expression evaluation
Compiler Support

C

  • XC16X/ST10 (Cosmic)
    • ELF/DWARF
  • GNU-GCC166 (HighTec)
    • DBX
  • C166 (Keil)
    • EOMF-166
  • C166 (TASKING)
    • IEEE

C++

  • GNU-CPP166 (HighTec)
    • DBX
  • CP166 (TASKING)
    • IEEE
Logical Display of Periperals
  • Display of onchip peripherals
  • User definable windows
  • Interactive window definition with softkey support
  • Pulldown menues for selection of choices
  • Additional description for each field
Script Language PRACTICE
  • Structured Language
  • Menu Support
  • Command Logs
  • Custom Menues
  • Custom Toolbars and Buttons
  • Custom Dialog Windows
  • 64-Bit Arithmetic
  • Numeric, Logical and String Operators
  • Direct Access to System States
NOR FLASH Programming
  • Internal and/or external NOR FLASH memories
  • All common NOR FLASH types
  • Programming of multiple NOR FLASH devices
  • Provided by debuggers and in-circuit emulators
NAND FLASH Programming
  • Generic and CPU-specific NAND FLASH controllers
  • Support all common NAND FLASH devices
  • Bad block treatment (skipped, reserved block area)
  • ECC generation
SIM Instruction Set Simulators
  • Easy high-level and assembler debugging
  • Interface to all compilers
  • Trace Buffer
  • Powerful script language
  • Software compatible to all TRACE32 tools
  • Hardware simulation
Trace-based Profiling
  • Detailed analysis of function run-times
  • Detailed analysis of task run-times and state
  • Graphical analysis of variable values over the time
  • Analysis of the time interval of a single event (e.g. Interrupt)
  • Analysis of the time interval between 2 defined events
Trace-based Code Coverage
  • Long-Time Hardware Coverage Analysis for Emulator and ETM
  • Trace Based Coverage Analysis for ICD and Emulator
  • Analysis on ASM and HLL
  • Coverage summary on modul/function level
Sample-based Profiling
  • Long-time performance analysis for functions
  • Long-time performance analysis for tasks
  • Long-time analysis of the contents of a variable or memory location and more
Logger
  • Software trace of any size stored in an array structure on the target
  • General trace format provided by TRACE32-PowerView
  • Configuration and display commands provided by TRACE32-PowerView
  • Works as trace with address and data information
  • Works as a program flow trace (SH4, PowerPC)
  • Time stamp possible
  • Predefined algorithms to fill the trace provided by Lauterbach
  • User defined algorithms to fill the trace also possible
Snooper
  • Samples memory while application is running
  • Support for special debug communication channels
  • All trace display and analysis functions can be used
  • Trigger on specific values
  • Dynamic performance analysis
RTOS
RTOS Support
3rd Party Integration
3rd Party Tool Integration
Help System
  • Acrobat Based Documentation
  • Fast Text Search
  • Device Specific Filtering
  • Basic and Advanced Help
  • Training Manuals Included
  • WWW Update




Copyright © 2010 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice.
Last generated/modified: Mar-10-2010