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Error Message "Emulation Memory Refresh Fail" (68360)
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Why does the message "emulation memory refresh fail" appears during change of the PLLCR register?
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The ICE-68360 configured with DRAM emulation memory may show this error message
at changing the PLLCR register.
Workaround:
SETUP.REFERR OFF
SYStem.TimeReq 10.ms
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Problems at PLL Register Modification (68360)
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Why does emulation crash when PLL registers are modified?
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The CPU stopps its clock for a while until the PLL is oscillating stable at the new clock frequency. For this reason the emulator will detect a "ClockFail", an "Emulation Debug Port Fail" or "Dual Port Fail".
Workaround:
Disable ClockFail detection
Increase TimeRequest value
Increase TimeDebug value
SYStem.Option TestClock OFF
SYStem.TimeReq 10.ms
SYStem.TimeDebug 10.ms
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Start-up (68360)
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The command "SYS.Up" does not work!
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The 68360 CPU disables the CLKO1 signal on MODCK0 = 1 .and. MODCK1 = 0.
Therefore the BDM clock cannot be generated by this clock. The TESTCLOCK option must be switched off.
Start-up sequence:
SYS.RES
SYS.O DC 1000000.
SYS.O TESTCLOCK OFF
SYS.O MODCK0 1
SYS.O MODCK1 0
SYS.UP
For correct trace the CLKO1 line should be switched to FULL.
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Trace Listing does not work (68360)
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What could be the reason if the trace listing does not work?
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The trace does not work if the CPU′s CLK01 line is disabled. Please set the "Clock Output 1 Mode" in the "CLKOCR" register to FULL.
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