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PDF document ( 78KB / 07-Sep-2016 )


09-02-15 (MICROBLAZE)

Ref: 0422
Why are there no peripheral files (.PER) for Xilinx FPGAs?

Peripheral files (.PER) correspond to the peripheral register of a concrete system implementation (i.e. they contain the registers for a memory controller, an I2C bus, an ethernet controller, etc.). In the case of FPGAs they have to correspond to the user's system design and are application specific. Therefore no generic .PER files are available for an FPGA type (e.g. Xilinx Kintex-7 XC7K325-T-2FFG900C). For information about creating custom .PER-files refer to the document "Peripheral Files Programming Commands" (per_prog.pdf).


Connection to Target Fails (MICROBLAZE)

Ref: 0291
Why does the connection to the target fails?

When connecting to XILINX targets be sure to use a recent version of the debug cable (see picture).
With the old version of the debug cable target connection will fail or be unreliable.


crt0.s not found (MICROBLAZE)

Ref: 0400
Why do I get the message Warning: file [...]\gcc\libgloss\microblaze\crt0.S not found

When creating programs with Xilinx EDK, the tool links some standard libraries with your code to create the executable. These standard libraries are built from files like crt0.S, crtinit.S etc. As they are created by Xilinx, the debug info contains paths to the source files specific to the Xilinx build machines. Usually these paths are not consistent with those on your machine.

To avoid the warning you can use the command sYmbol.SOURCEPATH.translate to have TRACE32 look in a different directory for the source file. To find out the paths associated with the currently loaded program use the command. sYmbol.List.SOURCE


y.sourcepath.translate "\proj\epdsw\gnu\mb_gnu\src\gcc\libgloss\microblaze" "c:\Xilinx\14.4\ISE_DS\EDK\sw\lib\microblaze\src"


Error Reading Processor Config Register (MICROBLAZE)

Ref: 0407
What can I do about "Error Reading Processor Config Register"?

The error message "Error Reading Processor Config Register" indicates that the basic communication with the MicroBlaze core could not be established.

Most of the time the error is caused by an incorrect JTAG configuration of TRACE32. For details please refer to the documentation of the commmands SYStem.Config IRPRE, SYStem.Config IRPOST, ...

Attention: For MicroBlaze there is one special case when the width of the IR is bigger than 6bits (e.g. for Virtex5FXT IRWIDTH = 10bits). In this case the IRPOST value needs to be adapted . For details please refer to section "Detecting multicore settings" in the document app_microblaze.pdf ("Connecting to MicroBlaze Targets for Debug and Trace") or contact Lauterbach support.


Fail of Single Stepping (MicroBlaze)

Ref: 0237
Single stepping sometimes fails with MB V4.00.a, MB V5.00.A. What can I do?

In MicroBlaze V4.00.a, V5.00.A there is a hardware issue that can lead to erroneous single stepping behavior. Solution: update to TRACE32 from December 2006 or later. This release works around the problem.


FPGA configuration via TRACE32 (MicroBlaze)

Ref: 0306
FPGA configuration via TRACE32 fails but works with Xilinx Impact

In one case it was observed, that FPGA configuration worked with Xilinx Impact but failed with TRACE32. In this case the target had been set up for FPGA configuration via SPI. This implies the possibility to override the configuration via JTAG.

After jumpering the target for "JTAG dedicated" configuration, downloading the bitstream via TRACE32 worked fine. Note that in the failing case the download failed silenty i.e. jtag.loadbit did not report an error.

In general be sure to set multicore pre/post parameters before configuring the FPGA with identical values as used for debugging.


Generating correct debug info (MicroBlaze)

Ref: 0391
Why are local variables displayed incorrectly?

When compiling MicroBlaze applications for debugging them with TRACE32, be sure to use the correct compiler options. The option "-g3" and DWARF2 debug info are recommended.

Note: The option "-g" creates debug info that is mostly intended for GDB and does not work well with TRACE32. The debugger will no be able to correctly display local variables, stack back trace etc.


Go.Up Command Fails (MicroBlaze)

Ref: 0241
Why does the Go.Up command fail inside interrupt handlers?

The Go.Up command (function key F6) may fail inside an interrupt, exception or break handler that is called via the brk or brki instructions. Use go.return to get to the end of the handler routine and leave it via step.asm until the PC is back in the interrupted routine.


Loading C++ programs (MicroBlaze)

Ref: 0272
I have problems loading C++ programs for Microblaze. Which parameters do I need?

For loading C++ programs for Microblaze that were generated with the Xilinx Tool chain use the Data.Load.ELF command with the parameters /cygdrive /gcc3 /gnucpp

In some cases it is necessary to execute the symbol.cleanup command (no parameters) after loading the .elf file.


d.load.elf filename.elf /cygdrive /gcc3 /gnucpp


MC Settings Calculation (MicroBlaze)

Ref: 0235
How are multicore settings calculated?

For a description of how to calculate multicore settings (PRE/POST values) for MicroBlaze cores, see the application note "Connecting to MicroBlaze Targets for Debug and Trace" (app_microblaze.pdf).


MicroBlaze spontaneously stops while debugging interrupts (MICROBLAZE)

Ref: 0341
MicroBlaze spontaneously stops while TRACE32 is attached

In some configurations of MicroBlaze using interrupts it was observed, that the core stopped without apparent reason, if TRACE32 was attached. Without the debugger, the program runs OK.

Apparently this is because MicroBlaze's mechanism for polling the run state can fail when the core takes an interrupt.

To work around the problem, move the SW break vector to an address far away from the interrupt handler (0x10) e.g. to the address 0x40. The distance should ideally be 24 bytes or more.

sys.o.BRKVECTOR 0x40 ; Attention: set this _before_ SYStem.UP


No Source Code shown on Xilinx Targets (MICROBLAZE)

Ref: 0214
Virtex: after loading an ELF file (PPC or Microblaze) to the target, no source code is displayed. Why?

The Xilinx compilers from the EDK operate inside a Cygwin environment and therefore create debug information with non-standard path names. Use the option /cygdrive when loading these ELF files: data.load.elf eventgen_ppc/executable.elf /CYGDRIVE


On-chip Data Breaks with unaligned Memory (MicroBlaze)

Ref: 0239
Why are the on-chip databreaks unaligned with memory?

There is a (mostly theoretical) problem with the on-chip breakpoint implementation in MBV4, MBV5 related to unaligned memory accesses. A "sw" or "lw" instruction (store word, load word) writing/reading address 0x2003 will automatically word-align its address to 0x2000 before executing. However, an on-chip breakpoint set at 0x2000 will _not_ detect this access. The case is largely theoretical because the MB compiler does not create this kind of access. If necessary, the problem can be worked-around by using an address range for the OnChip as in "break.set 0x2000--0x2003 /read". (Note the "--" double minus for range specifiation).


On-chip Databreak Problem (MicroBlaze)

Ref: 0238
MB V4.00.a: OnChip Data Breaks do not work as expected

Microblaze MB V4.00.a has a hardware issue that affects use of on-chip breaks. When specifying a read or write data value, the OnChip break logic does not consider the width of the access. Therefore avoid using the /data.byte, /data.word, /data.long options. Simple read/write on-chip breaks that do not specify a data value work.
The hardware issue is fixed in MB V5.00.b.


Problems with Source Code Display (MicroBlaze)

Ref: 0236
Why does not the debugger display the source code associated with my program?

The Xilinx Microblaze compiler is based on the GNU GCC and the Cygwin toolset. Therefore file paths in the debug information in the .ELF file are generated in a non-standard form e.g. as /cygdrive/c/sample instead of
Use the option /CYGDRIVE for enabling automatic path conversion:
    Data.LOAD.ELF MBSample/sample.elf /CYGDRIVE


Setting Register R0 fails (MicroBlaze)

Ref: 0240
Why does the setting of register R0 fail?

The architectural register R0 in Microblaze is hardcoded to 0. Therefore changing the register value to other values will fail.


Software Breakpoints or Single Stepping fail with ucLinux (MicroBlaze)

Ref: 0259
Why do software breakpoints or single stepping fail with ucLinux for MicroBlaze?

Because the initialization code for ucLinux overwrites the breakpoint handler, single stepping and software breakpoints will fail after starting the ucLinux kernel.
Use the command
SYStem.Option BrkVector 0x70
to specify an alternative location for the breakpoint handler.


Target Connection (MicroBlaze)

Ref: 0234
How should I connect the target? Why does connection to ML310 fail?

For connecting to the target use the included adapter together with the debug cable. The adapter plugs into the 14-pin connector of the target board. This port is also used to configure the FPGAs via the Xilinx download cable and often labelled as "FPGA&CPU Debug" or "PC4 JTAG".
For debugging Microblaze on Xilinx EVB ML310 always use the "PC4 JTAG" connector. The "CPU JTAG" connector will not work.
NOTE: Even though Microblaze and PPC405 use the same debug cable there is a difference regarding target connections: Microblaze cores are always debugged via the 14 pin header, whereas PPC405 cores (embedded in some Xilinx FPGAs) are occasionally accessed via other connectors.


Trace Interface for MicroBlaze (MicroBlaze)

Ref: 0243
Is there a trace interface for Microblaze cores?

Lauterbach supports a real-time trace for the Xilinx MicroBlaze core up to MicroBlaze V7. The trace provides up to 512MB of external high speed trace memory, which is used instead of scarce on-chip memory resources for storing the trace information. Features included are: program flow and data trace as well as statistical analysis of function and task run-times, variables access, code coverage and more.


XPS demo applications do not work (MICROBLAZE)

Ref: 0340

Many of the demo applications generated by the XPS (Xilinx platform studio) give feedback via printf(). Therefore be sure to open a terminal window in TRACE32, otherwise the application will appear to fail working, because it is blockes waiting for the debugger to read the output data. Use the following sequence to open a terminal window
term.res              ; be sure to reset terminal functionality
term.method mdmuart
term.size 110. 1000.  ; make T32 poll the target for text output


No Source Code shown on Xilinx Targets (PPC440)

Ref: 0214
Virtex: after loading an ELF file (PPC or Microblaze) to the target, no source code is displayed. Why?

The Xilinx compilers from the EDK operate inside a Cygwin environment and therefore create debug information with non-standard path names. Use the option /cygdrive when loading these ELF files: data.load.elf eventgen_ppc/executable.elf /CYGDRIVE

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Last generated/modified: 22-Sep-2016