Connection to Target Fails (MICROBLAZE) |
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Why does the connection to the target fails? |
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When connecting to XILINX targets be sure to use a recent version of the debug cable (see picture). With the old version of the debug cable target connection will fail or be unreliable. 
Debug Cable Versions (282K)
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Fail of Single Stepping (MicroBlaze) |
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Single stepping sometimes fails with MB V4.00.a, MB V5.00.A. What can I do? |
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In MicroBlaze V4.00.a, V5.00.A there is a hardware issue that can lead to erroneous single stepping behavior. Solution: update to TRACE32 from December 2006 or later. This release works around the problem. |
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Go.Up Command Fails (MicroBlaze) |
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Why does the Go.Up command fail inside interrupt handlers? |
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The Go.Up command (function key F6) may fail inside an interrupt, exception or break handler that is called via the brk or brki instructions. Use go.return to get to the end of the handler routine and leave it via step.asm until the PC is back in the interrupted routine. |
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Loading C++ programs (MicroBlaze) |
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I have problems loading C++ programs for Microblaze. Which parameters do I need? |
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For loading C++ programs for Microblaze that were generated with the Xilinx Tool chain use the Data.Load.ELF command with the parameters /cygdrive /gcc3 /gnucpp Example: d.load.elf filename.elf /cygdrive /gcc3 /gnucpp |
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MC Settings Calculation (MicroBlaze) |
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How are multicore settings calculated? |
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For a description of how to calculate multicore settings (PRE/POST values) for MicroBlaze cores see the application note "Connecting to MicroBlaze Targets for Debug and Trace" (app_microblaze.fm)
Application Note (138K)
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No Source Code shown on Xilinx Targets (MICROBLAZE) |
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Virtex: after loading an ELF file (PPC or Microblaze) to the target, no source code is displayed. Why? |
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The Xilinx compilers from the EDK operate inside a Cygwin environment and therefore create debug information with non-standard path names. Use the option /cygdrive when loading these ELF files: data.load.elf eventgen_ppc/executable.elf /CYGDRIVE |
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On-chip Data Breaks with unaligned Memory (MicroBlaze) |
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Why are the on-chip databreaks unaligned with memory? |
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There is a (mostly theoretical) problem with the on-chip breakpoint implementation in MBV4, MBV5 related to unaligned memory accesses. A "sw" or "lw" instruction (store word, load word) writing/reading address 0x2003 will automatically word-align its address to 0x2000 before executing. However, an on-chip breakpoint set at 0x2000 will _not_ detect this access. The case is largely theoretical because the MB compiler does not create this kind of access. If necessary, the problem can be worked-around by using an address range for the OnChip as in "break.set 0x2000--0x2003 /read". (Note the "--" double minus for range specifiation). |
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On-chip Databreak Problem (MicroBlaze) |
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MB V4.00.a: OnChip Data Breaks do not work as expected |
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Microblaze MB V4.00.a has a hardware issue that affects use of on-chip breaks. When specifying a read or write data value, the OnChip break logic does not consider the width of the access. Therefore avoid using the /data.byte, /data.word, /data.long options. Simple read/write on-chip breaks that do not specify a data value work. The hardware issue is fixed in MB V5.00.b. |
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Problems with Source Code Display (MicroBlaze) |
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Why does not the debugger display the source code associated with my program? |
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The Xilinx Microblaze compiler is based on the GNU GCC and the Cygwin toolset. Therefore file paths in the debug information in the .ELF file are generated in a non-standard form e.g. as /cygdrive/c/sample instead of
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Setting Register R0 fails (MicroBlaze) |
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Why does the setting of register R0 fail? |
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The architectural register R0 in Microblaze is hardcoded to 0. Therefore changing the register value to other values will fail. |
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Software Breakpoints or Single Stepping fail with ucLinux (MicroBlaze) |
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Why do software breakpoints or single stepping fail with ucLinux for MicroBlaze? |
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Because the initialization code for ucLinux overwrites the breakpoint handler, single stepping and software breakpoints will fail after starting the ucLinux kernel. Use the command SYStem.Option BrkVector 0x70 to specify an alternative location for the breakpoint handler. |
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Target Connection (MicroBlaze) |
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How should I connect the target? Why does connection to ML310 fail? |
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For connecting to the target use the included adapter together with the debug cable. The adapter plugs into the 14-pin connector of the target board. This port is also used to configure the FPGAs via the Xilinx download cable and often labelled as "FPGA&CPU Debug" or "PC4 JTAG". For debugging Microblaze on Xilinx EVB ML310 always use the "PC4 JTAG" connector. The "CPU JTAG" connector will not work. NOTE: Even though Microblaze and PPC405 use the same debug cable there is a difference regarding target connections: Microblaze cores are always debugged via the 14 pin header, whereas PPC405 cores (embedded in some Xilinx FPGAs) are occasionally accessed via other connectors. |
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Trace Interface for MicroBlaze (MicroBlaze) |
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Is there a trace interface for Microblaze cores? |
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Lauterbach supports a real-time trace for the Xilinx MicroBlaze core up to MicroBlaze V7. The trace provides up to 512MB of external high speed trace memory, which is used instead of scarce on-chip memory resources for storing the trace information. Features included are: program flow and data trace as well as statistical analysis of function and task run-times, variables access, code coverage and more. |
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Copyright © 2008 Lauterbach Datentechnik GmbH, Fichtenstr. 27, D-85649 Hofolding, Germany Impressum The information presented is intended to give overview information only. Changes and technical enhancements or modifications can be made without notice. Last generated/modified: Aug-27-2008 |
Connection to Target Fails (MICROBLAZE)
FAQ for BDM-MICROBLAZE
