The ECC8 is a low cost, high-performance module for emulation and logic analysis.
It is fully compatible to the TRACE32 bus system and may work together with all
8 bit probes and some 16 bit probes when emulating the 8 bit derivates.
A hierarchical symbol database enables structured symbolic debugging. Symbol names
can be up to 255 significant characters long and can be used to show single program
addresses, module names and memory classes. With 2 Mbyte of free memory (within the
System Control Unit), approximately 60000 symbols may be loaded. The disassembler
can use the symbols for labels and/or operands.
High-Level Language Debugging
The high-level debugger can support all common high-level languages but includes
special support for PL/M, C, PASCAL and ADA in that it recognizes and uses all
data types. The screen display can be in assembler, high-level or a mixture of
the two. It is possible to construct both assembler and high-level windows on
the screen simultaneously. All variable types specific to the high-level language
can be displayed and modified. Addresses can be absolute, relative or line number
A newly developed multitasking debugger is provided which allows up to 16 processes
or independent programs to be run simultaneously. Each task can be defined as a
foreground or background task. For systems that require certain aspects of their
operation to be maintained at all times (e.g. interrupts, timer operations etc),
the background programs can be executed so that these real-time dependencies can
be serviced. The foreground task is then debugged in the normal manner but even
when not executing the foreground task, the background programs still operate
in real- time.
The editor window can be synchronised to the debugging window so that when an
error is found, the source text can immediately be shown and if required,
edited. Also during debugging, it is possible to place markers in the source
text at appropriate points so that all corrections can be made at the same time,
but later. When the source text is reopened, the system will present each line
marked for correction in sequence.
The on-screen assembler is provided in place of the more common line assembler
found on other systems. With the on-screen assembler, short programs can be
written quickly and reliably. It is not a full assembler whose output code is
linkable in the usual way to the main program.
Separate Emulation Control Processor
The emulator is controlled by a separate processor with approximately 1 MIPs
performance. Functions such as task changing or memory refresh are done
independently of the main system controller or the emulation CPU.
2 Emulator Operating Modes
- Stand Alone Mode
The emulator operates without being connected to the target system. In this
mode all emulator capabilities can be used to debug software.
- Active Mode
The emulator operates with the target system (with internal or external clock).
This mode provides the ability to test software and hardware using all the
functions of TRACE32.
A step mode is provided whereby the emulator simply steps the CPU instruction by
instruction as fast as it can. In this mode, operating speed of the target is
reduced by a factor of approximately 100, but all register values are available
at each step.
Bus Structure for 8 Bit CPU up to 16 Mbyte
High Clock Frequency
Because of the compact, layered construction, bus lengths are kept to a minimum
and clock frequencies of 30MHz are possible for the support of fast 8 bit CPUs.
Memory Orientated Breakpoint System with up to 16 Mbyte Breakpoint Memory
Most currently available emulators use multiple address and data comparators to
form the breakpoint system. This technique not only restricts the number of
breakpoints available it also means that systems using bank selection are difficult
to support. The breakpoint, memory on the TRACE32 is basically a bytewide
memory structure that can be mapped in a similar way to the overlay memory.
When any memory location is accessed, the corresponding breakpoint byte is also
accessed so that there are effectively 8 kinds of breakpoints for each
8 Breakpoint Types
In each group there are up to 16 million breakpoints available depending upon the
amount of breakpoint ram fitted. Breakpoints can be specified as a single address
or an address range. Each breakpoint group can be made task specific so that for
example, they are only operative during foreground program execution on
- Program Breakpoint
- High-Level Breakpoint
- Spot Breakpoint
- Data Read Breakpoint
- Data Write Breakpoint
- General Purpose Point A
- General Purpose Point B
- General Purpose Point C
Hardware Support for High-Level Language Debugging
By using a specially reserved bit in the breakpoint memory, high-speed debugging of systems using high-level languages is available.
Memory Test on Power up with Access Time Test
After turning on the system, an optional memory test can be performed on both
emulation and breakpoint memories. The maxinium access time of the system can
be measured prior to beginning a debug session.
Support for External Bank Switching (up to 256 banks)
External bank switching schemes or MMUs can be supported by the memory mapper.
For this there are separate probe inputs to the emulator. This option is only
sensible on CPUs with less than 16 Mbyte addressing range.
Support for EPROMs with Inbuilt Paging
EPROMs of the types 27513 or 27011 are supported without external logic.
The address area within the EPROM has to be defined by the user, so that the
emulator can support the device.
Support for Dynamic Memory in the Target System
In order to refresh target dynamic ram when the emulation is stopped, a memory
refresh function is provided. The address range and memory class over which the
refresh occurs can be defined.
Selective Mapping of Memory Classes (CODE, EXTERNAL, etc)
The address mapper can segment the memory into 2 segments. Using this segmentation,
it is possible for example to split the memory such that a PROGRAM area can be mapped
to the emulators ram whilst the EXTERNAL area remains mapped as target memory. It
is also possible to have totally separate physical memory areas displayed
Memory Mapping in 4K Blocks and bytewise
The main mapping of memory is done in 4K blocks. However within two address ranges
8 long mapping can also be performed downto a single byte resolution (useful for
Memory Mapping Functions
- Static Emulation RAM
- Dynamic Emulation RAM
- Static Breakpoint RAM
- Dynamic Breakpoint RAM
- Flag RAM
0 to 250 wait cycles can be specified within any particular address range.
Access Protection and Write Protection
Data access in specific address areas can be prevented. Using this feature for
example, it is possible to prevent an I/O access occurring at a specific address
(if bytewise mapping is operative).
Most Emulation Functions can be used whilst the target CPU is running ('on the fly' operation)
Dual-Ported Access to all Emulation Memory
The whole emulation memory system (emulation and breakpoint memory) in dual-ported.
This allows the emulator to read or write memory whilst the target system is running
in real-time e.g. to show variables, port contents etc. For low to medium speed CPU clock frequencies (e.g. 8 MHz Z180) there is no degradation in performance of the
target system due to the operation of the dual-port access mechanism. At higher
CPU clock frequencies, the performance may be slightly reduced in accordance with
the number of accesses made by the control system. The dual-port access mechanism
can be switched off, but if this is done, then memory access by the emulator can
only take place when the target program is stopped.
Maximum 16 Mbyte Emulation RAM and 16 Mbyte Breakpoint RAM
In order to store programs in the emulator during the development phase, the address
space of the emulator can be as high as 16 Mbyte. This memory can be implemented
using static or dynamic rams.
128/512 Kbyte Memory on Board
- 128/512 Kbyte emulation memory
- 128/512 Kbyte break memory
- 128/512 Kbyte flag memory
Slot for 2 Mbyte Static Emulation and Breakpoint Memory
In the ECU module, up to 2 Mbyte of memory may be fitted. This can be user defined
to be either emulation memory or breakpoint memory.
In a special memory, all addresses which are read or written are marked with read
or write flags. This memory therefore can supply a lot of important information:
- Detection of uninitialised memory.
- Reading of uninitialised memory can be forced to generate an automatic break or to trigger the trace analyzer.
- Systematic program test due to the fact that each executed module will be marked in the flag ram.
- Detection of unused or unexecuted code.
- Systematic system test through visible code coverage analysis.
- Detecting accesses to unused or illegal address locations.
8 trigger/status outputs are provided. These outputs are mainly intended for
triggering or controlling certain functions within the target system. External
analyzers can be triggered using the Trace Analyzer outputs.
- Analyzer trigger output
- Emulator RUN signal
- Address signal from the breakpoint memory
- Pulse generator output
- Reset output (hardware reset for target system)
System Clock Generator
Cycle time programmable from 10 us to 10ms. Expiry of the timeout period can be
made to generate an emulator break.
Strobe Monitor for Target System
If the strobe period becomes bigger 10 us the system will alert the user.
If programmed to do so, the emulator can go into a standby mode if this occurs.
A trigger delay between the trigger event and the emulation break can be specified
in terms of time, a cycle count or trace cycle count.
The triggering can either stop the target CPU or only the analyzers data capture.
- Time delay 100ns to 300 days
- Cycles 0 to 2.8 E+14
- Trace cycles 0 to 2.8 E+14
Break Event Sources
- Exception break (e.g. RESET, NMI etc)
- Analyzer break A
- Analyzer break B
- Bus timeout
- high-level breakpoint
- Normal breakpoint
- General purpose breakpoint A
- General purpose breakpoint B
- General purpose breakpoint C
- Data read breakpoint
- Data write breakpoint
Internal Frequency Generator
- Variable VCO with frequency range from 1 to 70 MHz.
- No phase change when frequency changed - this can be used to test the limiting frequencies of the target system. Output available for direct connection to the target system (BNC).
- Emulation CPU clock frequency programming is done via the emulation control unit.
Integrated Universal Counter
- Frequency 0 to 20MHz
- System clock 0 to 80MHz
- Pulse width 100ns to 300 days
- Positive or negative edge count
- 0 to 2.8E + 14
- Use for measuring of internal and external signals like cycle frequency, CPU clock frequency, interrupt frequency etc.
- Data transfer rates
- Interrupt rates
- System performance
Slave StopMaster/Slave Synchronisation of several Emulators and Analyzers
Each of the following functions can be enabled or disabled individually:
In the slave mode the emulator follows whichever instrument is defined as the master.
In the master mode, the emulator controls all other emulators designated as slaves.
The sychronisation timing error between individual instruments is less thn 1us.
- Master Start
- Master Stop
- Slave Start
- Slave Stop
Program runtime is recorded automatically.
- Time from initial start
300ns to 300 days
- Time from last breakpoint
100ns to 300 days
- Time difference between 3 refs
300ns to 300 days
- Timers can be interrogated at any time and their values displayed
Inbuilt Pulse Generator
- Pulse output 50 Ohm/ 5V
- Output level static HIGH, LOW, LOWPULSE or HIGHPULSE.
- Pulse width 100ns to 6.5ms
- Single shot mode via keypress
The status of all the trigger settings are visible within their own window and can be modified 'on the fly'.
Trace with 88 Trace Channels
- 24 bit address
- 8 bit data
- 8 bit extendet data
- 8 bit status signals
- 16 bit universal channels (interrupt, ...)
- 2 bit markers
- 2 bit 4 trigger levels
- 8 bit external trigger inputs
- 1 bit DMA access
- 11 bit reserved (RUN, ....)
High-Speed 150ns Cycle Time
Large Trace Depth (32 KFrames)
Trace Memory Depth programmable from 0.1 K to 32 K
Two Operating Modes - FIFO and STACK
In the PRESTORE mode, the analyzer if only sampling data transfers samples always
the previous opfetch cycle.
Freely defined Markers can also be recorded to highlight specific Routines
Internal Expansion Capability
For emulator modules which need more trace capacity, the necessary extra bits
are built into the emulator module itself (e.g. 64 additional channels with
the trace board on microcontroller emulation haeds).
External Trigger Inputs
- 1 inputs with 8 channels
- 2 trigger qualifiers for each trigger level
- Static levels of the trigger inputs can be read at any time
- Free format definition of external trigger events
Free Format Definition of Data Events
Data events can be specified with constants, masks, range or boolean formulae.
Data events may be 8 or 16 bit events. To build 16 bit events 2 sucessive cycles
are analyzed at the same time (ranges, masks).
Hex and Mnemonic Display of Trace Data
Tracking of high-level Source Lines in the Listings
Time Correlation available with Logic Timing Analyzer
- 2 freely programmable outputs
- BNC connector for oscilloscope trigger
Analyzer Trigger Unit with 4 Levels
Analyzer Programming via a special Window
The programming of this complex trigger unit is done in an assembler like language
for maximum flexibility. Using this language, the programming of very complex
trigger sequences or operations can be defined.
Symbolic Operations for Analyzer Programming
All output operators and input variables can be input in symbolic form.
The target program symbols can also be used.
- 3 address ranges
- 2 data events (mask, range, ASCII, hex, binary)
- 2 external trigger events
- CPU state (MEM READ, IO WRITE, INTA, ...)
- Counter output
- Out (Target Stimulation)
- GOTO level
Free Format Definition of Data, Address and Trigger Events
Time, Event or external Clock Measurements with up to 3 Counters
There are two 16 bit counters for event measurement or event triggering. The counter
may be used as one 32 bit counter to build time windows or as one 32 bit
retriggerable delay counter. One counter is only event counters where access
to the counter status from the trigger sequences is not allowed. 2 counters
are retriggerable and can be evaluated as part of an expression in the trigger sequences. Each counter can be programmed as a timer for timing measurements or
an event counter (external clock).
2 universal counters - 16 bit
- Event count 1 to 65535
- Cycles 1 to 65535
- Time 0 to 6.5ms
- Selective release
- Trigger event when counter is zero
- Definition of time and event windows
- May be used as one 32 bit counter
All Counters can be read `on the fly'
A Display of the count values, the trigger values, the trigger levels and the
trigger flags is available in the trigger monitor window.
The Time Stamp Unit tags each trace record with a time value. These values are
absolute and sychronised with all the other time values within the TRACE32 system.
- Recording depth max. 32K
- 40 time stamp recording channels
- Resolution 100ns
- Maximum measuring time 1d
- Min. and max. time
- Include and exclude time
- Min. and max. times
- Execution time
- Response time
Performance Analyzer Resolution
Performance Analyzer Modes
Performance Address Ranges
- Address ranges