CombiProbeMIPI60-Cv2


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Tool Configuration
Adaptation
TRACE32 Debug Features
Details and Configurations


CombiProbeMIPI60-Cv2
  Highlights
CombiProbe MIPI60-Cv2 provides debug and system trace capability
Support for standard JTAG, debug HOOKs and I2C bus
Support for merged debug ports (two JTAG chains per debug connector)
Support for survivability features (threshold, slew rate, etc.)
Support for system trace port with up to 8 trace data channels
128 MByte of trace memory
Voltage range 1.0 V to 1.8 V

SMP debugging (including hyperthreading)
AMP debugging with other architectures
BIOS/UEFI debugging with tailor-made GUI for all UEFI phases
Linux- and Windows-aware debugging
Hypervisor debugging
Support for system trace decoding via the IntelĀ® Trace Hub Library


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List of Supported Compilers
List of Supported Target Operating Systems
List of Supported UEFIs
List of Supported Hypervisors




 
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Tool Configuration


Configuration of CombiProbe for Intel

The photo on the left side shows a standard configuration. The extended configuration shown on the right side allows to record additionally IntelĀ® Processor Trace data conveyed off-chip.

 
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Adaptation


Adaptation for CombiProbe MIPI60-Cv2

 
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TRACE32 Debug Features


Multicore Debugging
  • Debugger for all cores of a multicore chip
  • Debugging of application cores, DSPs, accelerator cores and special-purpose cores
  • Debugging of more than 80 core architectures
  • Support for every multicore topology
  • Support for all multicore operation modes
  • Support for AMP and SMP systems
  • Single debug hardware can be licensed for all cores of a multicore chip

Debug Support for Unified EFI Bootloader
  • Support by a loadable extension
  • Debug support for all UEFI phases
  • Tailor-made display windows for each UEFI phase
  • Continuous solution without "debug gap"
  • Debugging from reset vector
  • Debugging of dynamically loaded drivers from their entry point

OS-aware Debugging
  • Real-time, non-intrusive display of RTOS system resources
  • Task stack coverage
  • Task related breakpoints
  • Task context display
  • SMP support
  • Task related performance measurement
  • Statistic evaluation and graphic display of task run times
  • Task related evaluation of function run times
  • PRACTICE functions for OS data
  • Easy access via RTOS specific pull-down menus
  • Support for all major RTOSes

Hypervisor-aware Debugging
  • Seamless debugging of the total system in stop-mode
  • Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
  • Machine ID allows the user to uniquely identify any virtual machine in the system
  • Machine ID provides full visibility of context of active and inactive virtual machines
  • OS-awareness can be loaded for each virtual machine

Script Language PRACTICE
  • Structured Language
  • Menu Support
  • Command Logs
  • Custom Menues
  • Custom Toolbars and Buttons
  • Custom Dialog Windows
  • 64-Bit Arithmetic
  • Numeric, Logical and String Operators
  • Direct Access to System States

 
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Details and Configurations




Intel and the Intel logo are trademarks of Intel Corporation or its subsidiaries in the U.S. and/or other countries.




Copyright © 2017 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 07-Sep-2017