Xtensa Debugger


The embedded tools company
Features
IDE - Integrated Development Environment
Adaptation
Details and Configurations


Xtensa Debugger
  Highlights
Full high-level and assembler debugging
Batch Processing
Support for Internal Triggers
Unlimited Software Breakpoints
Target voltage 0.4 .. 5.0 V
Core Reset detection
Little- and Big-Endian support
Fast download (ETHERNET, PARALLEL, USB)
Support for TENSILICA
Support for CUSTOM_CPU, CUSTOM_DSP, DC_108MINI, DC_212GP, DC_232L, DC_330HIFI, DC_454CK, DC_570T, HIFI, XTENSA_9, XTENSA_LX2, XTENSA_LX3, XTENSA_LX4, XTENSA_LX5, XTENSA_LX6, XTENSA_LX7


Link Dim
Modules
Adaptions
Dimensions
Volt
Operation Voltage
Order
Order
Information
Support
Technical Support
[ip.cadence.com]  Tensilica IP Page at cadence


Demo Software for Download
TOP

Features


Full Memory Access

  • Display/Read/Write of target memory
  • Set/Delete Breakpoints
  • Full access to Auxiliary memory space

Variable Debug Clock Speed

  • 10 kHz...50 MHz
  • about 2/3 core clock
  • Variable up to 100 MHz (PowerDebug only)

High-Speed Download

  • 50 KByte/sec @ 12MHz core clock

 
TOP

IDE - Integrated Development Environment


 
TOP

Adaptation


Adaptation for Xtensa

Half-Size Adapters for Debuggers
  • 100 mil to 50 mil Adapters
  • Small Footprint for Target Connector

 
TOP

Details and Configurations


 
DIAMOND_CORES
DC_108MINITensilica
DC_212GPTensilica
DC_232LTensilica
DC_330HIFITensilica
DC_454CKTensilica
DC_570TTensilica
 
XTENSA_CUSTOM
CUSTOM_CPUTensilica
CUSTOM_DSPTensilica
HIFITensilica
XTENSA_9Tensilica
XTENSA_LX2Tensilica
XTENSA_LX3Tensilica
XTENSA_LX4Tensilica
XTENSA_LX5Tensilica
XTENSA_LX6Tensilica
XTENSA_LX7Tensilica




Copyright © 2017 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 07-Sep-2017