ARMv8 Debugger


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ARMv8 Debugger
  Highlights
Full support for all CoreSight components
Full architectural debug support

Support for 64-bit instruction set and 32-bit instruction sets ARM and THUMB
32-bit and 64-bit peripherals displayed on logical level
Support for 32-bit and 64-bit MMU formats
Auto-adaption of all display windows to AArch32/AArch64 mode

Ready-to-run FLASH programming scripts
Virtualization support
Bare metal and OS-aware debugging
Multicore debugging
Seamless debugging of big.LITTLE systems based on Cortex®-A57/Cortex®-A53, Cortex®-A72/Cortex®-A53, Cortex®-A73 or Cortex®-A35
AMP debugging with DSPs, GPUs and other accelerator cores
Support for 32-bit and 64-bit semi-hosting
Other TRACE32 tools for ARMv8: Debugging of Virtual Targets, On-chip trace support (ETB, ETF, ETR), Off-chip trace tools (ETMv4)
Support for
 AMCC, AMLOGIC, ARM, BROADCOM, CAVIUM, HISILICON, MARVELL, NVIDIA, NXP, QUALCOMM, RENESAS, SAMSUNG, XILINX

88F3710, 88F3720, 88F7020, 88F7040, 88F8020, 88F8040, APM883204-X1, APM883208-X1, APM883308-X1, APM883408-X1, APM883408-X2, BCM2837, BCM4908, BCM5871, CN81XX, CN83XX, CORTEX-A32, CORTEX-A35, CORTEX-A53, CORTEX-A57, CORTEX-A72, CORTEX-A73, CORTEX-R52, EXYNOS5433, EXYNOS7420, EXYNOS7570, EXYNOS7580, EXYNOS7870, EXYNOS8890, EXYNOS8895, FALKOR, KIRIN620, KRYOA, LS1012A, LS1043A, LS1046A, LS1088A, LS2080A, LS2088A, PXA1908, PXA1918, PXA1928, PXA1936, R8A77950, R8A77960, S32V234, S905, TEGRAX1, ZYNQ-ULTRASCALE+


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Information
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Technical Support
Ready-to-run bring-up scripts


[www.arm.com]  CoreSight On-chip Debug & Trace IP




 
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ARMv8 Ecosystem


Compiler Support

C

  • ARMCC (ARM)
  • AIF
  • ELF/DWARF
  • REALVIEW-MDK (ARM)
  • ELF/DWARF2
  • GCCARM (FSF)
  • COFF/STABS
  • ELF/DWARF2
  • GREENHILLS-C (GREENHILLS)
  • ELF/DWARF2
  • ICCARM (IAR)
  • ELF/DWARF2
  • ICCV7-ARM (IMAGECRAFT)
  • ELF/DWARF
  • CARM (KEIL)
  • ELF/DWARF
  • HIGH-C (SYNOPSYS)
  • ELF/DWARF
  • TI-C (TI)
  • COFF
  • GNU-C (WINDRIVER)
  • COFF
  • D-CC (WINDRIVER)
  • ELF

C++

  • ARM-SDT-2.50 (ARM)
  • ELF/DWARF2
  • REALVIEW-MDK (ARM)
  • ELF/DWARF2
  • GCCARM (FSF)
  • COFF/STABS
  • GNU (FSF)
  • EXE/STABS
  • GCCARM (FSF)
  • ELF/DWARF2
  • GREENHILLS-C++ (GREENHILLS)
  • ELF/DWARF2
  • MSVC (MICROSOFT)
  • EXE/CV5
  • HIGH-C++ (SYNOPSYS)
  • ELF/DWARF

C/C++

  • XCODE (APPLE)
  • Mach-O
  • GCC (HIGHTEC)
  • ELF/DWARF
  • VX-ARM (TASKING)
  • ELF/DWARF2
RTOS
RTOS Support (64-bit)
RTOS
RTOS Support (32-bit)
3rd Party Integration
3rd Party Tool Integration
 
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Adaption


Adaption for ARM Debug Connector

Adaption for MIPI Debug Connectors (ARM)

 
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More TRACE32 Tools for ARMv8


Debugging of Virtual Targets
  • Front-end to third-party virtual targets
  • Front-end to third-party core simulators
  • Front-end to third-party target servers
  • Front-end to TRACE32 Back-End
  • Same GUI as TRACE32 hardware debuggers
  • Debug features as provided by third-party software/TRACE32 Back-End
  • Trace features as provided by third-party software/TRACE32 Back-End
  • Windows, Linux and MacOSX
  • Reprise RLM floating licenses

On-Chip Trace (ETB, ETF, ETR)
  • Compatible to external ETM Trace
  • Readout through JTAG
  • No Speed Limit
  • Full Trace of Code and Data

Off-chip Parallel Trace (ETMv4)
  • Up to 4 GByte trace buffer
  • Target voltage 1.2 .. 3.3 V
  • 5 ns time stamp
  • Program and data trace
  • Performance analysis
  • Function and task run-time measurement
  • Code coverage
  • Support for Embedded Trace Macrocell (ETM), Program Trace Macrocell (PTM)
  • Support for Embedded Trace Buffer (ETB), Trace Memory Controller (TMC), Trace Port Interface Unit (TPIU)
  • Support for multiple trace sources in a single stream (CoreSight trace)

Off-chip Serial Trace (ETMv4)
  • Support of High-Speed Serial Trace Port (ETM-HSSTP, ARM specified)
  • Compatible to Xilinx Aurora protocol
  • Support of up to four differential lanes
  • Maximum 6,25Gbit/s lane speed
  • Up to 4 GByte trace buffer size, sufficient for up to 24 Giga CPU cycles

 
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TRACE32 Debug Features


Multicore Debugging
  • Debugger for all cores of a multicore chip
  • Debugging of application cores, DSPs, accelerator cores and special-purpose cores
  • Debugging of more than 80 core architectures
  • Support for every multicore topology
  • Support for all multicore operation modes
  • Support for AMP and SMP systems
  • Single debug hardware can be licensed for all cores of a multicore chip

Logical Display of Peripherals
  • Display of onchip peripherals
  • User definable windows
  • Interactive window definition with softkey support
  • Pulldown menues for selection of choices
  • Additional description for each field

NOR FLASH Programming
  • Internal and/or external NOR FLASH memories
  • All common NOR FLASH types
  • Programming of multiple NOR FLASH devices
  • Provided by debuggers and in-circuit emulators

NAND FLASH Programming
  • Generic and CPU-specific NAND FLASH controllers
  • Support all common NAND FLASH devices
  • Bad block treatment (skipped, reserved block area)
  • ECC generation

High-Level-Language Debugging
  • Supports multiple languages
  • Full support for C++
  • Integrated into TRACE32 environment
  • Supports most compilers and hosts
  • Same user interface on different hosts
  • High speed download
  • Debugs optimized code
  • Display of function nesting
  • Display of linked lists
  • Powerful expression evaluation

Full MMU Support
  • Full integrated support of processor's MMU
  • Display of processor MMU registers
  • Display of MMU table entries
  • Display of address translation table
  • 'Shadowing' MMU address translation inside debugger
  • Full virtual and physical access to target at any time
  • Debugger has optionally write access to write protected memory areas
  • Detection and decoding of software MMU tables built by operating systems
  • Support for several user space MMU tables side by side
  • TLB context tracking and git statistics via CTS

OS-aware Debugging
  • Real-time, non-intrusive display of RTOS system resources
  • Task stack coverage
  • Task related breakpoints
  • Task context display
  • SMP support
  • Task related performance measurement
  • Statistic evaluation and graphic display of task run times
  • Task related evaluation of function run times
  • PRACTICE functions for OS data
  • Easy access via RTOS specific pull-down menus
  • Support for all major RTOSes

Hypervisor-aware Debugging
  • Seamless debugging of the total system in stop-mode
  • Hypervisor-awareness as a loadable debug extension is provided by Lauterbach
  • Machine ID allows the user to uniquely identify any virtual machine in the system
  • Machine ID provides full visibility of context of active and inactive virtual machines
  • OS-awareness can be loaded for each virtual machine

Sample-based Profiling
  • Long-time performance analysis for functions
  • Long-time performance analysis for tasks
  • Long-time analysis of the contents of a variable or memory location and more

Script Language PRACTICE
  • Structured Language
  • Menu Support
  • Command Logs
  • Custom Menues
  • Custom Toolbars and Buttons
  • Custom Dialog Windows
  • 64-Bit Arithmetic
  • Numeric, Logical and String Operators
  • Direct Access to System States

 
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Details and Configurations






Copyright © 2017 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice. Report Errors
Last generated/modified: 04-May-2017