Adaption for Nios II


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Debugger Adaption for NIOS II
Trace Adaption for NIOS II




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Debugger Adaption for NIOS II


Connector 10 pin


Signal

Pin

 Pin

Signal

    
TCK12GND
TDO34VTREF
TMS56N/C
N/C78RST-
TDI910GND
    


TCK Jtag Clock. It is recommended to put a pull-DOWN to GND on this signal.
TMS Jtag TMS. It is recommended to put a pull-UP to VCC on this signal.
TDI Jtag TDI. It is recommended to put a pull-UP to VCC on this signal.
TDO Jtag TDO. (No pull-up, or pull down is needed for this signal.)
VTREF Reference voltage. This voltage should indicate the nominal HIGH level for the JTAG pins. So for example, if your JTAG signals have a voltage swing from 0V - 3.3V, the VTREF pin should be connected to 3.3V.
RST- Optional. This pin is not used at the moment and is intended for future use:
If your board has a low active CPU reset signal, you can connect this low active reset signal to this pin. The debugger can drive this pin to GND to hold the CPU in the reset state. The debugger drives this pin as open-drain, so a pull-up is mandatory.

Dimension

Connector Type

  • This is a standard 10 pin double row (two rows of 5 pins) connector (pin to pin spacing: 2.54mm/0.100").
  • If terminal strip without shroud is used, the spacing marked with "A" must be a minimum of 20.5mm/0.8".


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Trace Adaption for NIOS II


Connector MICTOR


Signal

Pin

 Pin

Signal

    
N/C12N/C
N/C34N/C
N/C56CLK
N/C78TRIGB
RST-910TRIGA
TDO1112VTREF
N/C1314N/C
TCK1516D11
TMS1718D10
TDI1920D09
N/C2122D08
N/C2324D07
N/C2526D06
D172728D05
D162930D04
D153132D03
D143334D02
D133536D01
D123738D00
    
Connect Pin 39,40,41,42 and 43 to GND


Signals for JTAG:
Only connect the JTAG signals on the MICTOR, iff you do not additionally have a 10 pin JTAG connector.
If you have both (a 10 pin connector for JTAG and a MICTOR), then only connect the trace signals to the MICTOR and leave the JTAG signals unconnected on the MICTOR. In this case the VTREF signal on the MICTOR indicates only the voltage level for the trace signals. The voltage level for the JTAG signals is then indicated by the VTREF signal on the 10 pin JTAG connector.
TCK Jtag Clock. It is recommended to put a pull-DOWN to GND on this signal.
TMS Jtag TMS. It is recommended to put a pull-UP to VCC on this signal.
TDI Jtag TDI. It is recommended to put a pull-UP to VCC on this signal.
TDO Jtag TDO. (No pull-up, or pull down is needed for this signal.)
RST- Optional. This pin is not used at the moment and is intended for future use:
If your board has a low active CPU reset signal, you can connect this low active reset signal to this pin. The debugger can drive this pin to GND to hold the CPU in the reset state. The debugger drives this pin as open-drain, so a pull-up is mandatory.
Signals for Tracing:
VTREF Reference voltage. This voltage should indicate the nominal HIGH level for the trace pins and JTAG pins (if JTAG pins are in use). So for example, if your signals have a voltage swing from 0-3.3V, the VTREF pin should be connected to 3.3V.
CLK Trace Clock.
D00 - D17 Trace Data.
If possible the PCB trace lengths of CLK and D00-D17 should have the same lengths, since this signals carry high frequency data.
TRIGA Optional. Trace Trigger. At the moment the trace logic of the Nios II core supports one trigger output. This output can be used to trigger actions of the external trace (for example stopping a trace recording).
TRIGB Optional. Trace Trigger. At the moment the trace logic of the Nios II core only supports one trigger output, so this pin is intended for future use. You might leave it unconnected, if you have not enough pins available on your FPGA.

Dimension





Order No

    AMP part numbers for suitable receptacles (for target)

    AMP 2-5767004-2 RoHS compliant
    Tyco Electronics





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Last generated/modified: 1-Aug-2016