In-Circuit Emulator for Motorola 68360/349
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ICE 68360 Base
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Picture
  Highlights
33 MHz zero-waitstate
On-circuit emulation mode
DRAM support
Dual-ported memory
Fast BDM interface
Dynamic data trigger
Interface with all Compilers
C++ support
CASE Tools Interface
RTOS Support
Windows9x, NT and Motif Interface
Support for MC68349, MC68360, MC68EN360, MC68MH360
 
  Introduction
The ICE-68360 module support all CPU32+ derivatives up to 33 MHz at 3.3V or 5V. The modular and open technology of the system allows the fast integration of new chip designs.

A hardware accellerator for the BDM allows fast download to target memory. The module includes a dynamic data trigger system, which generates valid trigger signals on multicycle data accesses.

A software compatible BDM debugger is available.

TRACE32-ICE is a state of the art In-Circuit Emulator, which offers unlimited hardware breakpoints and up to 16MByte dual-ported emulation memory. The real-time trace and trigger work up to the max. speed of the CPU. The analyzer offers selective trace as well as performance analysis and statistic functions.

TRACE32 works with the highest variety of host interfaces. The communication link to the host is done by the printer port, a fibre optic interface or ethernet allowing a high-speed transfer.


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ice68360.pdf
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ICE 68360 Base

Operating Modes

  • Reset Down
  • Reset Up
  • Alone Internal
  • Alone External
  • Emulation Internal
  • Emulation External

Dual-Port Access

  • Request
  • Denied

Max. Operation Frequency 33 MHz

  • 25 MHz 0 wait state
  • 33 MHz 1 wait state

Internal Clocks

  • VCO
  • 5/10/20 MHz (EXTAL)
  • 32 KHz
  • VCO/100
  • VCO*2

Clock System

  • Operation with external or internal clock
  • Internal clock (EXTAL) 2 to 70 MHz

Wait System

  • Additional wait cycles (1-15) can be specified
  • Up to 250 wait cycles (4K blocks global and bytewise)

Voltage and Clock Monitors for the Target System

Emulation System uses BDM Interface

  • Hardware based protocoll generator for max. debug speed
  • 10 MHz max. transfer speed

DMA Modes

  • Trace
  • Transparent

Exception Control

  • Static Exception Simulation
  • RESETH Processor
  • RESETH Target
  • HALT
  • BUSREQ
  • Exception Control
  • RESETH
  • RESETS
  • HALT
  • BUSERR
  • BUSREQ
  • Exception Trigger
  • RESETH
  • RESETS
  • HALT
  • BUSREQ
  • BUSERR
  • Simulation
  • Exception Simulation
  • RESETH
  • RESETS
  • HALT
  • BUSERR
  • BUSREQ

40 Additional Trace Channels

Full 32 Bit Address Mapping with Premapper

  • 32 bit
  • 28 bit
  • 24 bit

Global Breakpoints

Dynamic Data Selector

  • Easy triggering on multi cycle, not aligned data transfers

Reset Configuration by Software

  • CONFIG
  • MODCK
  • BW16

Support for On-Circuit Emulation

Power Consumption

  • 15 W




Copyright © 2010 Lauterbach GmbH, Altlaufstr.40, D-85635 Höhenkirchen-Siegertsbrunn, Germany  Impressum
The information presented is intended to give overview information only.
Changes and technical enhancements or modifications can be made without notice.
Last generated/modified: 26-Feb-2010